Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method

An anti-single event and circuit technology, applied in the field of field editable gate arrays, can solve problems such as high circuit complexity and controller instability, and achieve the effects of low complexity, low power consumption, and high inheritance

Active Publication Date: 2014-09-17
CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides an anti-single-event flipping circuit and method for reloading configuration commands and configuration data using an external controller to solve the problems of high circuit complexity and instability in the controller. SRAM type FPGA refresh circuit and refresh method

Method used

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  • Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method
  • Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method
  • Single event upset resistant SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refresh circuit and refresh method

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specific Embodiment approach 1

[0022] Specific implementation mode 1. Combination figure 1 and figure 2 Describe this embodiment, the SRAM type FPGA refresh circuit resistant to single event flip; including BOOT memory and SCRUB memory. The BOOT memory stores the user function modules. The normal loading of the FPGA is completed through the data line and the control line after power-on. When the loading is completed, the FPGA refresh module will periodically control its corresponding I / O port. The I / O port is connected to the SCRUB memory. The control terminal is connected, so that the configuration file in the SCRUB memory is periodically loaded into the FPGA. The file stored in the SCRUB memory is the modified configuration file in the BOOT memory. Before loading, the file may affect the normal operation of the FPGA. The configuration command is reset or deleted, so the FPGA keeps working normally. If a single event flip occurs in the FPGA refresh module, the FPGA can be reloaded to ensure the normal op...

specific Embodiment approach 2

[0026] Specific embodiment 2. Combination image 3 Describe this embodiment, this embodiment is the refresh method of the SRAM-type FPGA refresh circuit resistant to single event inversion described in the specific embodiment 1, and the method is realized by the following steps:

[0027] 1. Use the burner to burn the complete configuration file to BOOT memory, and at the same time burn the refresh configuration file to SCRUB memory;

[0028] 2. The system is powered on, the FPGA clears the internal configuration data, and waits for the initialization to complete;

[0029] 3. The FPGA initialization is successful, the BOOT memory starts to configure the data, and the configuration method selects the Salve SelectMap method;

[0030] 4. T 1 After milliseconds, the BOOT memory data configuration is completed, the enable signal is set low, the chip select signal is set high, the memory is disabled, the internal address counter is cleared, and the data output port is in a high-imp...

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Abstract

The invention relates to the field of spatial single event upset resistance of an FPGA (Field Programmable Gate Array), and particularly relates to a single event upset resistant SRAM (Static Random Access Memory) type FPGA refresh circuit and a refresh method, aiming at solving the problems such as high circuit complexity and controller instability as an existing SRAM type FPGA refresh circuit and a method utilize an external controller for achieving the reloading of a configuration command and configuration data. Two same memories are adopted, a complete configuration file is stored in a BOOT, the configuration file contains a functional module to be realized by a user and a refresh module for realizing refresh of the FGPA, an edited configuration file is stored in an SCRUB, after the FPGA loads the first memory, the refresh module is started to enter a refresh mode, and periodical refresh of the FPGA under normal working is achieved by periodically reading the configuration file in the SCRUB memory. The single event upset resistant SRAM type FPGA refresh circuit and the refresh method provided by the invention have the advantages that the power consumption for FPGA refresh and the circuit complexity are effectively reduced.

Description

technical field [0001] The invention relates to the technical field of field editable gate arrays, in particular to a refresh circuit and a method for realizing an SRAM type FPGA anti-single event flipping by using two pieces of memory. Background technique [0002] FPGAs based on static random access memory (SRAM) are widely used in aerospace due to their diverse and repeatable functional configuration, small application size and short R&D cycle. The FPGA with anti-fuse configuration is more susceptible to the single event effect (SEE), but its outstanding advantages make it still undertake the arduous tasks of attitude control, data transmission and image processing of the aircraft in the space environment, and gradually become a trend [0003] Due to the great influence of high-energy particles in space, the logic state of the internal configuration memory of SRAM-type FPGA is often flipped due to particle impact, that is, single-particle flip occurs. If the flip occurs...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/413
Inventor 冯汝鹏徐伟郑晓云朴永杰王绍举徐拓奇金光
Owner CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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