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Method for processing a carrier

A carrier and additional layer technology, used in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., which can solve the problem of micro-load dependence on aspect ratio

Active Publication Date: 2014-09-17
INFINEON TECH DRESDEN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Applying etching processes such as plasma etching or e.g. reactive plasma etching, while having many advantages, can also have the problem of possible loading mechanisms (loading effects) such as microloading or aspect ratio dependent etching

Method used

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  • Method for processing a carrier
  • Method for processing a carrier
  • Method for processing a carrier

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0015] The following detailed description refers to the accompanying drawings that show, by way of illustration, embodiments and specific details in which the invention may be practiced.

[0016] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments or designs.

[0017] The word "above" as used with reference to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "directly on" (eg, in direct contact with) the implied side or surface. The word "above" as used in reference to a deposited material formed "over" a side or surface may be used herein to mean that the deposited material may be formed "indirectly on" the implied side or surface, with one or more additional layers Arranged between the implied side or surface and the...

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PUM

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Abstract

A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

Description

technical field [0001] Various embodiments generally relate to a method for processing a carrier. Background technique [0002] Fabricating an integrated circuit, a chip or a die or machining a carrier may include at least one etching process in order to generate the desired shape of the structural elements. Applying etching processes such as plasma etching or, for example, reactive plasma etching, while having many advantages, may have the problem that loading mechanisms (loading effects) such as microloading or aspect ratio dependent etching may occur. Thus, a hole (or notch) with a larger open area contained in an integrated circuit on a carrier may end up having a greater depth than another hole (or another notch) with a smaller open area, regardless of The very same etching process was used for the two holes (or the two notches). Thus, the distance between adjacent structural elements on the wafer as well as the size of the structural elements can affect the etch rate...

Claims

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Application Information

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IPC IPC(8): H01L21/336
CPCH01L21/28506H01L21/308H01L21/3083H01L29/66795H01L21/845H01L21/823431H01L21/823821H01L21/0223H01L21/02255H01L21/0273H01L21/3065H01L21/3081H01L21/823437H01L21/823462
Inventor M.伦克S.特根
Owner INFINEON TECH DRESDEN