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Array substrate, manufacturing method thereof, and display device

A technology of an array substrate and a manufacturing method, which is applied in the field of liquid crystal display, can solve the problems of reducing the aperture ratio of pixels, disordered arrangement of liquid crystals, and large height difference, and achieves the effects of reducing the aperture ratio of pixels, increasing the range, and reducing the step difference.

Active Publication Date: 2017-02-15
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, in the process of fabricating the array substrate with five patterning processes, since a separate patterning process is not used to form the pattern of the active layer, except for the channel region, there is an active layer under the source and drain metal layers. As a result, in the effective display area, the height of the film layer at the data line formed by the source-drain metal layer has a relatively large gap with the film layer height of the adjacent area. liquid to make the arrangement of liquid crystal molecules orderly), and the area near the data line on the array substrate is not easy to be rubbed, which will cause the liquid crystal arrangement in the area near the data line to be disordered. Once there is no BM (Black Matrix , black matrix), light leakage will occur, but if BM is set to cover this area, the aperture ratio of the pixel will be reduced

Method used

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  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device

Examples

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Embodiment 1

[0095] In this embodiment, the level difference compensation pattern is formed by using the gate metal layer, and the gate electrode, the gate line and the level difference compensation pattern are simultaneously formed through one patterning process.

[0096] Figure 4 is a schematic plan view of the array substrate of this embodiment, Figure 5 for Figure 4 A-B cross-sectional schematic diagram of the array substrate shown, from Figure 4 and Figure 5 It can be seen in the figure that a level difference compensation pattern formed by the gate metal layer is provided under the edge of the data line, Figure 5 The number of film layers under the alignment layer 17 at positions 1, 2, 3, 4, and 5 is 4, 3, 4, 5, and 6 in sequence. It can be seen that it is because of the existence of the level difference compensation pattern that the level difference of the film layer no longer like figure 2 In that way, jumping directly from 4 to 6, a step structure is formed at the edge...

Embodiment 2

[0108] In this embodiment, the active layer is used to form the level difference compensation pattern, and the pattern of the active layer and the level difference compensation pattern are simultaneously formed through one patterning process.

[0109] Figure 7 is a schematic plan view of the array substrate of this embodiment, Figure 8 for Figure 7 A-B cross-sectional schematic diagram of the array substrate shown, from Figure 7 and Figure 8 It can be seen in the figure that a level difference compensation pattern formed by the active layer is provided under the edge of the data line, Figure 8 The number of film layers under the alignment layer 17 at positions 1, 2, 3, 4, and 5 is 4, 3, 4, 5, and 6 in sequence. It can be seen that it is because of the existence of the level difference compensation pattern that the level difference of the film layer no longer like figure 2 In that way, jumping directly from 4 to 6, a stepped structure is formed at the edge of the da...

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Abstract

The invention provides an array substrate, a manufacturing method thereof, and a display device, belonging to the field of liquid crystal displays. The array substrate includes a substrate and a first region and a second region adjacent to the substrate, the level difference between the first region and the second region exceeds a threshold, wherein a level difference compensation pattern is arranged on the substrate, and The level difference compensation pattern overlaps both the first region and the second region in a direction perpendicular to the substrate, and the level difference compensation pattern does not exceed the first region and the second region. The technical solution of the present invention can reduce the level difference between the data line and the adjacent area on the array substrate, thereby increasing the rubbing range of the polyimide liquid during the rubbing process, without reducing the pixel aperture ratio , reduce the risk of light leakage.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] As a mainstream wide viewing angle technology of TFT-LCD (Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display), planar electric field technology has the advantages of ultra-wide viewing angle, high aperture ratio, and low response time. In the current planar electric field technology, the array substrate is generally produced by using six patterning processes, and there are many production processes, resulting in a higher production cost of the array substrate; in order to reduce the production cost of the array substrate, HTM (HalfTone Mask, half-tone mask) or SSM (Single Slit Mask, single slit mask) for patterning, to form the pattern of the active layer and the pattern of the source and drain metal layer at the same time in one patte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/84G02F1/1333
CPCH01L27/1244H01L27/1288H01L29/42384H01L27/124H01L27/1259H01L29/78606H01L29/42372H01L29/78696
Inventor 高山
Owner BOE TECH GRP CO LTD