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clock gating circuit

A clock gating, gate circuit technology, applied in logic circuits, logic circuits with logic functions, and power reduction through control/clock signals, etc., can solve problems such as power consumption of clock gating units, reduce power consumption, reduce efficacy effect

Active Publication Date: 2017-12-12
MEDIATEK SINGAPORE PTE LTD SINGAPORE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Therefore, power loss is an important issue in existing clock gating cells

Method used

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Embodiment Construction

[0016] As mentioned above, standard clock gating cells consume a lot of power even if they are not enabled. Therefore, the object of the present invention is to provide a clock gating circuit. Compared with the existing clock gating unit, the clock gating circuit of the present invention consumes only a small amount of power.

[0017] Please refer to image 3 , which is an embodiment of the clock gating circuit of the present invention. In order to prevent the transistors in the clock gating circuit 300 from being triggered by the clock signal before the clock gating circuit 300 is enabled, the present invention reduces the number of clock signals in the clock gating circuit, and these clock signals are used as the input of the transistors. In order to achieve the above purpose, the clock gating circuit 300 does not have an inverter for generating the inverted clock signal CKZ and an inverter for generating the clock signal CK1, wherein the phase of the clock signal CK1 is s...

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Abstract

The invention discloses a clock gating circuit, which is used to generate a clock enable signal according to a clock input signal and a logic enable signal, comprising: a first transistor group, connected in series between a power supply and ground, for receiving the logic enable signal and generate the first output; the second transistor group is connected in series between the power supply and the ground to receive the first output and generate the second output; the third transistor group is connected in series to the Between the power supply and the ground, used to receive the second output and the inverted second output; and an AND gate circuit, used to receive the second output and when the logic enable signal is logic 1, generate the A clock enable signal; wherein the gate of one transistor in the first transistor group, the second transistor group and the third transistor group receives the clock input signal. The clock gating circuit disclosed by the invention can greatly reduce power consumption without reducing performance or affecting circuit space.

Description

technical field [0001] The present invention relates to an electronic circuit, in particular to a clock gating circuit with low power consumption. Background technique [0002] Current microchips use clock gating cells to save power consumption. The central processing unit in the microchip operates according to a clock signal. For example, the clock signal is generated by a phase locked loop (PLL). The clock signal is called root clock, which is used to control the modules in the microchip. When the module in the microchip does not need to be used, the clock input of the module is cut off through the clock gating cell connected to the root clock, and the clock gating cell is controlled by the enable signal (enable signal) The logic level generates the clock output. Please refer to Figure 1A , which is a schematic diagram of an existing clock gating unit. As shown, the clock gating unit 100 includes an active-low latch circuit 120 . The active low latch circuit 120 rec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K19/00
CPCH03K5/135H03K19/20H03K19/0013H03K19/0016
Inventor 苏曼·凯特·古路拉加劳
Owner MEDIATEK SINGAPORE PTE LTD SINGAPORE