Clock gating circuit

Abstract

The invention discloses a clock gating circuit for generating a clock enable signal with respect to a clock input signal and a logic enable signal. The clock gating circuit includes: a first pluralityof transistors, serially connected between a power supply and the ground, for receiving the logic enable signal and generating a first output; a second plurality of transistors, serially connected between the power supply and ground, for receiving the first output and generating a second output; a third plurality of transistors, serially connected between the power supply and ground, for receiving the second output and an inverted second output; and an AND gate circuit, for receiving the second output and generating the clock enable signal. The clock gating circuit substantially lowers powerconsumption and may not lower energy efficiency and affect circuit space.

Description

technical field [0001] The present invention relates to an electronic circuit, in particular to a clock gating circuit with low power consumption. Background technique [0002] Current microchips use clock gating cells to save power consumption. The central processing unit in the microchip operates according to a clock signal. For example, the clock signal is generated by a phase locked loop (PLL). The clock signal is called root clock, which is used to control the modules in the microchip. When the module in the microchip does not need to be used, the clock input of the module is cut off through the clock gating cell connected to the root clock, and the clock gating cell is controlled by the enable signal (enable signal) The logic level generates the clock output. Please refer to Figure 1A , which is a schematic diagram of an existing clock gating unit. As shown, the clock gating unit 100 includes an active-low latch circuit 120 . The active low latch circuit 120 rec...

AI Technical Summary

Problems solved by technology

[0007] Therefore, power loss is an important issue in existing clock gating cells

Images