A Multi-phase Clock Generation Circuit with Programmable Function

Abstract

The invention provides a multi-phase clock generation circuit with programmable functions, including a multi-phase clock generation circuit and a programmable phase selection circuit; the multi-phase clock generation circuit includes a voltage-controlled delay line, a phase detector, a charge pump, a low-pass filter, bias voltage generator; the voltage-controlled delay line includes a plurality of identical voltage-controlled delay units connected in series, the input end is connected to an external reference clock, and the output end outputs a delayed clock signal; the phase detector is sensitive to the external reference clock and delay The clock signal performs phase discrimination and outputs rising and falling signals; the charge pump performs charging and discharging operations on the low-pass filter according to the rising and falling signals; the bias voltage generator is used to control the voltage output by the low-pass filter, An adjustable bias voltage is provided for the voltage-controlled delay unit; a programmable phase selection circuit generates an output clock signal with an adjustable phase according to clock signals input to it from a plurality of voltage-controlled delay units. The invention has simple structure and low cost.

Description

technical field [0001] The invention relates to a clock generation circuit, in particular to a multi-phase clock generation circuit with programmable functions. Background technique [0002] High-performance and low-cost signal acquisition and processing systems are in great demand in industrial measurement and control fields such as automatic measurement, equipment detection, and safety monitoring. Compared with a CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) signal processor, a CCD (Charge-coupled Device, Charge-Coupled Device) signal processor has obvious advantages in terms of sensitivity, resolution, noise control, and the like. Because the optimal working timing of CCD devices changes with the change of working conditions, the phase difference between the phase clocks in the traditional CCD signal processor is fixed, and it is impossible to adjust the clock signals such as CCD device reset and correlated double sampling. As a ...

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Problems solved by technology

[0003] The main purpose of the present invention is to provide a multi-phase clock generation circuit with programmable functions, which overcomes the fixed phase difference between the phase clocks in the traditional CCD signal processor, and cannot adjust the clock signals such as CCD device reset and correlated double sampling. The problem

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