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Double-groove junction-isolated voltage clamping device and method for forming the same

A trough area, p-type technology, applied in the field of double trough area junction isolation voltage clamping devices, can solve problems such as interruption, surface charge accumulation, gate oxide breakdown, etc.

Active Publication Date: 2017-04-12
ANALOG DEVICES INT UNLTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

High power dissipation can increase the temperature of the IC and can cause problems such as gate oxide breakdown, junction damage, metal damage and surface charge build-up
Furthermore, transient electrical events can induce latch-up (in other words, the inadvertent creation of a low-impedance path), thereby interrupting the operation of the IC and possibly causing permanent damage to the IC

Method used

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  • Double-groove junction-isolated voltage clamping device and method for forming the same
  • Double-groove junction-isolated voltage clamping device and method for forming the same
  • Double-groove junction-isolated voltage clamping device and method for forming the same

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Embodiment Construction

[0023] The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be implemented in many different ways as defined and covered by the claims. In this description, reference is made to the drawings, wherein like reference numerals may indicate identical or functionally similar elements.

[0024] Certain electronic systems can include pins that operate at relatively higher voltages than ground or a power low supply, but where the voltage difference is relatively small under normal signaling conditions. For example, an electronic system can include two or more interface pins that operate at voltage levels near the maximum rated handling voltage (e.g., 60V or greater), but these interface pins are usually relatively small from each other. Operate at a voltage difference of less than about 5V (eg, a voltage difference of less than about 5V).

[0025] It can be shown that conventional...

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PUM

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Abstract

Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Description

technical field [0001] Embodiments of the present invention relate to electronic systems, and more particularly, to dual-slot junction-isolated voltage clamping devices for protecting low voltage circuits connected between high voltage interface pins. Background technique [0002] Some electronic systems may be exposed to transient electrical events, or relatively short duration electrical signals with rapidly changing voltages and high power. Transient electrical events can include, for example, electrical overload / electrostatic discharge (EOS / ESD) events caused by a sudden discharge of electrical charge from an object or person to an electronic system. [0003] Transient electrical events can damage integrated circuits (ICs) within electronic systems due to overvoltage conditions and / or high levels of power dissipation within relatively small areas of the ICs. High power dissipation can increase the temperature of the IC and can cause problems such as gate oxide breakdown...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02H01L29/87H01L21/8248
CPCH01L27/0262H01L21/761H01L27/027H01L27/0817H01L29/1083H01L29/1087H01L29/66121H01L29/7436H01L29/87
Inventor J·A·塞尔瑟多D·J·克拉克J·G·费法
Owner ANALOG DEVICES INT UNLTD