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A processing method, device and system for pcie link failure

A link fault and processing method technology, applied in the field of data transmission, can solve the problems of channel width reduction, channel width uncertainty, affecting channel transmission performance, etc., and achieve the effect of reducing the size of the channel number

Active Publication Date: 2017-06-20
HUAWEI TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of this, the present invention provides a fault handling method, device and system for a PCIe link, so as to overcome the existence of the channel width obtained through renegotiation due to the limitation of the channel number of the channel in which the fault occurs in the prior art. Uncertainty and the possibility that the channel width will be greatly reduced, which will seriously affect the transmission performance of the channel

Method used

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  • A processing method, device and system for pcie link failure
  • A processing method, device and system for pcie link failure
  • A processing method, device and system for pcie link failure

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Embodiment Construction

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

[0050] The invention provides a new PCIe (Peripheral Component Interconnect Express) device link fault processing method. A PCIe node device is a general term for devices that use the PCIe protocol for data transmission. The PCIe node device may be a chip integrated in an independent device, or may be a physically independent device, which is not limited here. For the connection relationship between PCIe node devices, please refer to the attached figure 1 . as attached figure 1 As shown, two PCIe node devices can be directly connected for data transmission. For example, the downlink port of the root complex (root complex) device is directly connected to the uplink...

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Abstract

The invention discloses a PCIe link failure processing method, device and system. When a PCIe node device detects a failure in the channel of the link between the downstream PCIe node device, it sends an MSI message to the CPU and communicates with the downstream PCIe node. The device negotiates the current channel width value; the CPU obtains the channel negotiation capability value M and the current channel width value M of the PCIe node device from the PCIe node device according to the MSI message, and compares N with M / 2.

Description

technical field [0001] The present invention relates to the technical field of data transmission, and more specifically, relates to a PCIe link failure processing method, equipment and device. Background technique [0002] Currently, in the field of data transmission technology, the PCIe (Peripheral Component Interconnect Express) protocol has been widely used. When the PCIe protocol is applied to devices, data is transmitted between devices in a point-to-point manner. Devices that use the PCIe protocol for data transmission are collectively referred to as PCIe node devices. In the system, the communication between two PCIe node devices can implement a link connection through a serializer / deserializer (serdes, Serializer / De-Serializer) circuit. When two PCIe node devices transmit data, the negotiated rate is used to transmit data through serdes. A link between two PCIe node devices can include 1, 2, 4, 8, 16 or 32 serdes. When there are multiple serdes, these serdes are ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/24H04L69/40H04L47/76H04L69/14
CPCG06F11/0745G06F11/3027G06F13/4221G06F13/4022G06F11/221
Inventor 杜阁
Owner HUAWEI TECH CO LTD
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