Method and test structure for characterizing the current noise tolerance of random access memory cells

Abstract

The invention provides a method and a test structure for characterizing current-resistant noise tolerance of a random access memory unit. The method for characterizing the current-resistant noise tolerance of the access memory unit comprises the following steps: scanning voltage of a first storage node of the unit to obtain a relation curve of the scanned voltage and power supply current; inversely scanning voltage of a second storage node to obtain a relation curve of the scanned voltage and the power supply current; superposing the two curves to obtain a curve crossing at three points; calculating current differentials between two side points and a middle point and taking a smaller value of the current differentials as a maximum current-resistant noise tolerance value of the unit. The invention also provides the test structure for characterizing the current-resistant noise tolerance of the random access memory unit. The method and the test structure for characterizing the current-resistant noise tolerance of the random access memory unit have the advantages of being intuitive, accurate in measurement and high in applicability.

Description

technical field [0001] The invention relates to the technical field of memory design and test, in particular to a method and test structure for characterizing the anti-current noise tolerance of a static random memory unit. Background technique [0002] Embedded Static-Random-Access-Memory (SRAM) is an important storage device in embedded electronic systems. With the development of integrated circuit technology towards deep submicron, the anti-noise ability of SRAM is a major indicator for evaluating its performance; the fluctuation of process parameters can not be ignored for SRAM units that require strict matching of tubes; therefore, it needs to be fully considered The noise immunity of the unit. [0003] N Curve (N Curve) is one of the commonly used methods to assess the ability of SRAM to resist current noise. The schematic diagram of the circuit structure for testing the anti-noise ability of ordinary SRAM in the way of N curve is as follows: figure 1 As shown: the ...

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Problems solved by technology

[0009] In view of the above-mentioned shortcoming of prior art, the object of the present invention is to provide a kind of method and test structure that characterizes SRAM unit anti-noise, be used to solve the test imprecise, test result of the test method of N curve in the prior art. Poor reliability and other issues

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