Distributed type SSM protocol processing system and method based on complex packet switching system

Abstract

The invention provides a distributed type SSM protocol processing system and method based on a complex packet switching system, and relates to the technical field of synchronous transmission systems. The distributed type SSM protocol processing system comprises a main control disc, a system switching unit and at least one service disc. The system switching unit is responsible for processing the communication between a main control processing unit and service processing units. The main control disc comprises the main control processing unit and a main control logic processing unit. The main control logic processing unit is responsible for collecting SSM input information of all ports of each service disc and packaging output data of the main control processing unit. The main control processing unit is responsible for processing the SSM input information. Each service disc comprises one service processing unit and a service logic processing unit, wherein the service processing unit is responsible for calculating the SSM input information of all the ports of the corresponding service disc and sending the SSM input information to the service logic processing unit, and the service logic processing unit is responsible for reporting the SSM input information of all the ports of the corresponding service disc to the main control logic processing unit and sending ESMC messages to all the corresponding ports.

Description

technical field [0001] The present invention relates to the technical field of synchronous transmission systems, in particular to a distributed SSM (Synchronous Status Message, Synchronous Status Message) protocol processing system and method based on a complex packet switching system. Background technique [0002] Currently, the SSM protocol is widely used in synchronous digital systems in the transmission field. For a synchronous system, clock synchronization is crucial, and avoiding timing loops in the clock topology design of a synchronous system is the primary consideration of the design. [0003] For how to avoid timing loops, the implementation of the SSM protocol is an important means. The implementation of the SSM protocol not only includes the implementation of SSM rules, but also has strict requirements on the time of SSM information processing. According to the requirements of G.8262 and national standard YD / T 1267, the SSM processing delay T under the conditio...

AI Technical Summary

Problems solved by technology

Timing loops occur when the slave clock output is looped back to the input directly or indirectly through the network), resulting in overall clock chain instability and oscillations in the clock chain

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