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semiconductor manufacturing method

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of unevenness, poor line width roughness, unfavorable device performance, etc., and achieve good consistency and simple process flow. Effect

Active Publication Date: 2017-08-25
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, in the current SADP process, the spacer deposition and etching process will lead to poor line width roughness (Line Width Roughness, LWR) phenomenon, such as figure 1 The shown line widths (a and a') and spacing (b and b') are not uniform, which will adversely affect the performance of the device

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  • semiconductor manufacturing method
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Embodiment Construction

[0040] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0041] At the same time, it should be understood that, for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0042] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way taken as limiting the invention, its application or uses.

[0043] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods and devices should be considered part of the Authoriz...

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Abstract

The invention discloses a semiconductor manufacturing method which relates to the technical field of self-aligning double patterning. The semiconductor manufacturing method comprises the steps of: providing a substrate on which an interface layer, a core film layer and a hard mask layer are successively deposited; patterning the hard mask layer and the core film layer for forming intermediate patterns, wherein the pattern interval of the intermediate patterns is determined according to a final pattern interval; performing transverse back-etching on the core film in the intermediate patterns, wherein the amount of the transverse back etching is determined according to a final key dimension; making SiGe perform epitaxial growth on the surface of the core film for filling a side wall space of the core film which is removed by transverse back etching; removing the hard mask; eliminating the core film for obtaining a spacer pattern mask which is formed by SiGe; and downwards transmitting patterns through a dry method. The semiconductor manufacturing method has an advantage of simple process flow and is a self-aligning double patterning method. Furthermore the final line width dimension and dimension consistency of the grooves between the lines can be better controlled.

Description

technical field [0001] The invention relates to the technical field of double patterning (Double Patterning), in particular to a semiconductor manufacturing method. Background technique [0002] With the development of semiconductor technology to smaller node technology, photolithography technology has become a bottleneck restricting development. The double patterning technology may be the final solution for the continuous reduction in size of IC (Integrated Circuit, integrated circuit) structure for mass production. [0003] Currently, there are three typical double patterning techniques: LELE (LITHO-ETCH-LITHO-ETCH, lithography-etch-lithography-etch); LFLE (LITHO-FREEZE-LITHO-ETCH, lithography-freeze- photolithography-etching); and spacer SADP (Self Aligned Double Patterning, self-aligned double pattern). [0004] LELE is a lithography step followed by an etch step, followed by a lithography step and an etch step. The above two photolithography steps are critical photol...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/0337H01L21/0338
Inventor 王新鹏张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP