Array substrate, manufacturing method thereof, and display panel

Abstract

An array substrate, a fabricating method thereof, and a display panel including the array substrate are provided. The array substrate includes a base substrate (1), a planarization layer (12), and a first electrode layer (13). The planarization layer (12) in on the base substrate (1) and has a plurality of protrusions (20) protruding away from the base substrate (1) and resulting in a plurality of grooves between adjacent protrusions (20). The first electrode layer (13) has at least a portion over the plurality of protrusions (20) of planarization layer (12).

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display panel including the array substrate. Background technique [0002] In order to satisfy consumers' pursuit of display quality, the resolution of liquid crystal display panels is getting higher and higher, resulting in lower and lower aperture ratios of products and increasing power consumption. [0003] figure 1 It is a structural schematic diagram of an existing array substrate, on which a flat layer 2, a first electrode layer 3, an insulating layer 4 and a second electrode layer 5 are sequentially arranged on a base substrate 1 (the "base substrate" here includes a thin film transistor array) . Wherein, the second electrode layer 5 includes a plurality of electrode strips 50 . [0004] The liquid crystals 7 used in existing high PPI (Pixels Per Inch, number of pixels per inch) products are generally po...

AI Technical Summary

Problems solved by technology

However, the thickness of the insulating layer 4 decreases every time The driving voltage can only be reduced by 0.5V. For high PPI products, the thickness of the insulating layer 4 itself is already very small, and the range of reducing the driving voltage by reducing the thickness of the insulating layer is very limited

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