FPGA (Field Programmable Gate Array) based lower limb rehabilitation equipment

A technology for rehabilitation equipment and lower limbs, which is applied in the field of medical devices and can solve the problem of not being able to collect index data of paralyzed patients.

Inactive Publication Date: 2015-01-28

天津市意欧风范科技有限公司

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AI-Extracted Technical Summary

Problems solved by technology

During the rehabilitation training of patients with paralysis of the lower extremities, it is necessary to use some rehabilitation equipment to recover slowly through regular exercise. However, in the process of...

Abstract

The invention discloses FPGA (Field Programmable Gate Array) based lower limb rehabilitation equipment and belongs to the technical field of medical equipment. The FPGA based lower limb rehabilitation equipment is used for solving the defect that the lower limb rehabilitation training for paralytic patients is difficult. The FPGA based lower limb rehabilitation equipment comprises an optical-electricity encoder, a photoelectric coupler, an FPGA chip, a USB (Universal Serial Bus) interface chip, an upper computer, a power source and a crystal oscillator. The FPGA based lower limb rehabilitation equipment has the advantages of collecting data of a patient during lower limb rehabilitation training in real time, collecting patient physical state index data and providing accordance for later rehabilitation.

Application Domain

Chiropractic devicesDiagnostic recording/measuring +1

Technology Topic

Patient physical stateElectricity +7

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Examples

Experimental program(1)

Example Embodiment

[0009] The specific embodiments of the present invention will be described below in conjunction with the drawings.

[0010] See figure 1 The FPGA-based lower limb rehabilitation equipment in the embodiment of the present invention includes a mechanical system, a photoelectric encoder, a photocoupler, an FPGA chip, a USB interface chip, a PC upper computer, a power supply, and a crystal oscillator.

[0011] The photoelectric encoder is installed on the mechanical system and can collect the displacement data of the lower limbs during movement, and transmit the data to the photocoupler through the input port of the photocoupler.

[0012] The photocoupler is used to reduce the voltage of the digital signal output by the photoelectric encoder, and the voltage is matched with the FPGA chip.

[0013] The FPGA chip is connected to the output port of the photocoupler. The FPGA chip selected in this embodiment is a Cyclone III EP3C series device of Altera Corporation, and its model is EP3C16Q240C8N. The chip uses a 240-pin PQFP package, the core voltage is 1.2V, the peripheral I/O power supply is 3.3V, has 15408 logic units, 56 M9K memory modules, the total number of memory is 504Kbit, and contains 56 multipliers. , 4 phase-locked loops (PLL) and 20 global clock networks, supporting a maximum number of user I/O pins of 160. These abundant on-chip resources, coupled with its flexible programming method, make this chip the most suitable choice for data acquisition systems with complex logic and storage and buffering capabilities.

[0014] FPGA chip includes CPU, FIFO buffer, PLL clock. The input end of the PLL clock is connected to a 50MHz temperature-compensated crystal oscillator. The 50MHz temperature compensated crystal oscillator is used to provide the clock signal.

[0015] The FPGA chip processes the data transferred from the photocoupler through the CPU and stores it in the FIFO buffer, and then transmits it to the PC host computer via the USB interface chip.

[0016] An embodiment of the present invention has been described in detail above, but the content is only a preferred embodiment of the present invention, and cannot be considered as limiting the scope of implementation of the present invention. All equal changes and improvements made in accordance with the scope of the application of the present invention should still fall within the scope of the patent of the present invention.

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