Chip sealing ring structure

Abstract

The invention provides a sealing ring structure of a chip. The sealing ring structure comprises an inner sealing ring and an outer sealing ring, wherein the inner sealing ring is arranged surrounding an integrated circuit area and is provided with an aluminum weld pad; the outer sealing ring is arranged surrounding the inner sealing ring; the inner sealing ring comprises one or more first sub sealing rings, one or more second sub sealing rings and first dielectric isolation rings, wherein the one or more first sub sealing rings are coupled to the aluminum weld pad and are arranged close to the outer sealing ring, and each first sub sealing ring comprises a group of sealing strips, which are arranged along the circumferential direction and are independent of one another, and dielectric isolation strips which are used for isolating adjacent sealing strips; the one or more second sub sealing rings are arranged close to the integrated circuit area; the first dielectric isolation rings are arranged between the first sub sealing rings and the second sub sealing rings, so as to isolate the second sub sealing rings from the aluminum weld pad and the first sub sealing rings. According to the sealing ring structure of the chip, the second sub sealing rings are isolated from the aluminum weld pad and the first sub sealing rings by using the first dielectric isolation rings, and the first sub sealing rings are isolated into the mutually-independent sealing strips by using the dielectric isolation strips, so that the defect that the integrated circuit area is failed due to short circuit is avoided.

Description

technical field [0001] The present application relates to the field of semiconductor manufacturing, in particular, to a sealing ring structure of a chip. Background technique [0002] In a semiconductor manufacturing process, a semiconductor chip including a semiconductor active device and an interconnection structure disposed on the device can be formed on a semiconductor substrate through processes such as photolithography, etching, and deposition. Usually, multiple chips can be formed on a wafer, and finally these chips are cut off from the wafer for packaging process to form an integrated circuit area. During the process of dicing the chip, the stress generated by the dicing knife will cause damage to the edge of the chip, and even cause the chip to collapse. Currently, in order to prevent the chip from being damaged during cutting, a sealing ring is provided around the active device area of ​​the chip. The sealing ring can block the stress generated by the dicing knife...

AI Technical Summary

Problems solved by technology

[0005] In order to solve the problem that the metal aluminum wire is easily connected to the aluminum pad of the inner sealing ring to cause a short circuit in the integrated circuit area, the application provides a chip sealing ring structure

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