FPGA verification method and system based on processor system

A processor system and verification method technology, applied in the field of chip design, can solve problems such as difficult to effectively debug and locate faults, and achieve the effects of optimization, resource saving, and rich scalability

Active Publication Date: 2015-02-18
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Abstract
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Problems solved by technology

[0004] The present invention provides an FPGA verification method and system based on a processor system, which is used to solve the problem that FPGA verification based on a processor system is difficult to effectively debug and locate faults in the prior art

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  • FPGA verification method and system based on processor system
  • FPGA verification method and system based on processor system
  • FPGA verification method and system based on processor system

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Embodiment Construction

[0020] The content of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0021] figure 1 Shown is the outflow diagram of the FPGA verification method based on the processor system provided by the preferred embodiment of the present invention. figure 2 Shown is a schematic diagram of an FPGA verification system based on a processor system provided by a preferred embodiment of the present invention. Please also refer to figure 1 and figure 2 .

[0022] like figure 1 As shown, the FPGA verification method based on the processor system provided by the preferred embodiment of the present invention includes the following steps: S1: the monitoring module monitors the processing of the feature protocol according to the configured protocol feature word to be monitored, if the feature is monitored When an error occurs in the processing of the protocol, the monitoring module locks the current state of the error processor, marks...

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Abstract

The invention discloses a field-programmable gate array (FPGA) verification method and system based on a processor system. The method comprises the steps that a monitoring module monitors the processing condition of a feature protocol according to a configured protocol feature word to be monitored, locks the current state of a processor with an error when the monitoring module monitors that an error occurs during feature protocol processing, marks the vector position corresponding to the processor with the error in a vector table, and sends an error report message to an interface module; the interface module acquires and outputs the protocol processing content of the processor with the error for analysis according to the received error report message. The FPGA verification method and system based on the processor system can solve the problems that in the prior art, effective debugging and failure positioning of FPGA verification of a processor system are hard to achieve.

Description

technical field [0001] The present invention relates to the field of chip design, in particular to a field-programmable gate array (Field-Programmable Gate Array, FPGA) verification method and system based on a processor system. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The complex architecture supports high-end server systems to achieve high-performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the verification of this type of control chip, the FPGA verification of the multi-chip system is essential. In this case, there are two important problems in multi-chip FPGA verification: First, the complex message transmission between chips is c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26
Inventor 赵元童元满李仁刚
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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