Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor

Abstract

The invention discloses a silicon carbide metal oxide semiconductor field effect transistor, comprising: source (1), gate (2), gate oxide layer (3), N+ source region (4), P+ contact region (5) , P well (6), N-epi layer (7), buffer layer (8), N+ substrate (9), drain (10), isolation dielectric (11) and additional N-type implanted JFET sub-region (12 ). The silicon carbide metal oxide semiconductor field effect transistor proposed by the present invention reduces the resistance of the JFET region by partially injecting an additional N-type into the JFET region of the device, and at the same time satisfies that the channel is not depleted, and is especially applicable to short-channel silicon carbide MOSFET devices middle. The SiC metal oxide semiconductor field effect transistor device prepared by the invention can be used in power switching power supply circuits, DC / DC, AC / DC, DC / AC converters and the like.

Description

technical field [0001] The invention relates to a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET), in particular to a silicon carbide metal oxide semiconductor field effect transistor introducing a partially doped JFET region. Background technique [0002] Silicon carbide materials have excellent physical and electrical properties, while SiC MOSFET devices have the advantages of fast switching speed and small on-resistance, and can achieve high breakdown voltage levels at small epitaxial layer thicknesses, reducing power switch modules. Small size, low energy consumption, and obvious advantages in power switches, converters and other application fields. [0003] In the design and application of SiC MOSFET devices, the extra N-type injection in the JFET region (for N-type MOSFET devices) can reduce the resistance of the JFET region, thereby reducing the on-resistance of the device; by introducing a self-alignment process, the channel length can ...

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Problems solved by technology

[0003] In the design and application of SiC MOSFET devices, the extra N-type injection in the JFET region (for N-type MOSFET devices) can reduce the resistance of the JFET region, thereby reducing the on-resistance of the device; by introducing a self-alignment process, the channel length can be effectively reduced, thereby reducing the channel length. However, when the above two optimization methods are used at the same time, since the higher doped N-type JFET region and its adjacent P-well region form a wider depletion region, it is easy to deplete the channel region , leading to failure of short-channel devices

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