Time sequence estimation method for FPGA (field programmable gate array) post-mapping net list

Abstract

The invention discloses a time sequence estimation method for an FPGA (field programmable gate array) post-mapping net list. The method includes the steps: determining the type of a single connecting wire between a source block unit and a collecting block unit according to types of the source block unit and the collecting block unit; searching the global delay range and the global congestion range of the single connecting wire in a timing model library file according to the type of the single connecting wire; calculating local congestion of the single connecting wire and determining the local congestion range and the local delay range of the single connecting wire according to the local congestion; calculating the delay value of the single connecting wire according to the local congestion range and the local delay range of the single connecting wire. Therefore, the highest working frequency of an FPGA before placement and routing can be estimated, a clock constraint file is generated and replaces clock constraint set by a user to serve as input of a placement and routing tool, and the better highest frequency can be obtained by fewer iteration times.

Description

technical field [0001] The invention relates to the field of chip layout, in particular to a method for timing estimation of netlists after FPGA mapping. Background technique [0002] The highest frequency that Field Programmable Gate Array (FPGA) software can achieve is a measure of the performance of the FPGA chip. It has a lot to do with the initial clock constraints set by the user. Different initial clock constraints may lead to The highest frequency finally achieved varies greatly, and FPGA timing estimation is generally performed after place and route. Doing FPGA timing estimation before layout and routing, due to the lack of on-chip physical location information of block units and routing resources, it is very difficult to achieve a small error. Research in this field is basically blank in the current industry. Contents of the invention [0003] The purpose of the present invention is to provide a method for timing estimation of the netlist formed after the gate-l...

AI Technical Summary

Problems solved by technology

Do FPGA timing estimation before layout and routing. Due to the lack of on-chip physical location information of block units and routing resources, it is very difficult to achieve small errors. Research in this field is basically blank in the current industry.

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