Asynchronous clock synchronization constraint method in chip design

Abstract

The invention relates to a novel theoretical method for synchronization constraint of an asynchronous clock in a chip design process. Aiming at the MCU and SOC scale chip circuit design, under the condition that a large number of asynchronous clocks inevitably exist, when timing constraint is carried out on the design, synchronous normalization processing is carried out on the asynchronous clock constraint in the design by adopting the concept and thought of synchronization, and thus the chip circuit is constrained. On the premise of meeting the design requirements, the iteration time of the chip design from logic synthesis to layout wiring back door-level simulation is reduced to the maximum extent, so that the time cost of the chip design is greatly reduced, and the chip marketing speed is increased. Through verification of a certain chip design, compared with a common chip constraint method, the advantages of the method are very obvious, and a very excellent effect is achieved.

Description

technical field [0001] The invention belongs to the field of chip design and implementation, and proposes a new theoretical method for synchronous design constraints on the asynchronous clock in the chip. Background technique [0002] The current chip design is developing in the direction of high integration and complex functions, especially the design of MCU and SoC. Multiple functional IP cores are integrated on one microchip to realize complex functions. This makes the clock structure of the chip extremely complex, not only increases the number of clocks, but also contains many asynchronous clocks, the existence of these asynchronous clocks makes the timing constraints of the design more difficult. In logic design, you should try to avoid using asynchronous clocks, or perform synchronous processing on asynchronous clocks. However, in the current actual design process of large-scale chips, asynchronous clocks are unavoidable. Once the constraints of an asynchronous clock...

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Problems solved by technology

However, in the current actual design process of large-scale chips, asynchronous clocks are unavoidable. Once the constraints of an asynchronous clock are mistaken due to omissions, it may cause problems in the timing of the design, which in turn leads to the failure of the entire design. Not only the loss of tape-out costs, but also the increase in product time costs, sometimes even catastrophic

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