A 1394 link layer transaction level model based on uvm

Abstract

The invention provides a 1394 link layer transaction-level model built on basis of the UVM (universal verification methodology). The model is provided with a handy control interface, allowing a user to easily simulate and verify various scenes designed. The model comprises a link layer request model, a link layer data packet model, an application layer data packet model, a link layer monitoring model and a global configuration table; when using the model, verifiers of the 1394 link layer and the 1394 application layer can work separately under no mutual influence, reusability is good, workload is significantly reduced for the verifiers, and chip verification progress is quickened.

Description

technical field [0001] The invention belongs to the technical field of SoC chip design and verification, and relates to a transaction-level modeling of a layered protocol, in particular to a UVM-based 1394 link layer transaction-level model. Background technique [0002] The IEEE-1394 protocol is a layered protocol, which is divided into application layer, link layer, and physical layer from top to bottom. In the process of developing different 1394 series chips based on this protocol, the verification of 1394 physical layer chips requires the development of 1394 link layer Model and 1394 bus network topology model, 1394 link layer model and physical layer model can form a variety of 1394 bus network topologies. In addition, the implementation of different application layer protocols requires different application layer models. The development of layered protocol models can be 1394 chain Therefore, it is very important to develop a transaction-level model that meets the 1394...

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Problems solved by technology

[0003] When transaction-level models are used as part of the chip verification environment to provide transaction-level incentives, in order to verify more function points and cover as many codes and functions as possible, it is often necessary to generate a large number of effective verification incentive sequences. Verilog-based When the 1394 link layer model is constructed by the method, the link layer and the application layer model on it are often implemented together, so that when different protocol verifiers modify their configuration or incentives, it is easy to affect the link layer or application layer, and this kind of The multiple incentive sequences provided by the model are independent of each other, and cannot be reused on the basis of existing verification sequences to form new verification items, and cannot be well combined with existing multiple verification sequences to form new verification sequences. Constraints have certain limitations, so the verifier needs more effort and time when writing the verification stimulus sequence using the model developed by this method

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