A fault-tolerant master-slave synchronous serial communication system based on fpga

Abstract

The invention provides a fault-tolerant master-slave synchronization serial communication system based on FPGA; the fault-tolerant master-slave synchronization serial communication system based on FPGA comprises a master station module, one or more slave station modules, and two serial communication links; each serial communication link comprises a synchronization clock channel and a data channel; the master station module and the slave station modules uses the synchronization clock transmitted by the synchronization clock channel for achieving synchronous receiving and the synchronous transmitting of serial data transmitted by the data channel. The fault-tolerant master-slave synchronization serial communication system based on FPGA uses the dual link fault-tolerant communication for increasing the reliability of the serial communication system, uses the synchronization clock for achieving the synchronous receiving and synchronous transmitting of the serial data, thereby increasing the transmission efficiency of the serial communication system; a channel selecting module selects one serial communication link for receiving the data, and achieves detection of the communication state of the other serial communication link, thereby achieving the real-time detection of the communication state of the serial communication links, and fault undisturbed switching of serial communication links.

Description

technical field [0001] The invention relates to fault-tolerant communication in industrial field applications, in particular to an FPGA-based fault-tolerant master-slave synchronous serial communication system. Background technique [0002] In the field of industrial control, with the continuous improvement of the technical level, various fieldbus technologies have been developed, such as PROFIBUS, CAN, etc., but the master-slave bus based on RS485 is still widely used because of its simplicity and maturity. [0003] RS485 two wires, using differential signal negative logic, +2V~+6V means "0", -6V~-2V means "1". The serial communication link design based on master-slave bus technology usually adopts figure 1 The topological structure in the form of a daisy chain is shown. There is one master node and multiple slave nodes in the topology structure. The number of slave nodes depends on factors such as transmission distance, transmission rate, cable quality, and electromagneti...

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Problems solved by technology

[0010] Aiming at the disadvantages of low reliability and low transmission efficiency of the common RS485-based single communication link, the present invention proposes a fault-tolerant master-slave synchronous serial communication system based on FPGA. Link automatic detection, automatic switching, improve the reliability of the serial communication system; adopt synchronous serial communication, improve the transmission efficiency of the serial communication system

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