Asynchronous decoder and asynchronous decoding method for BMC (Biphase Mark Coding) signal

A decoder and signal technology, which is applied in the field of asynchronous decoders, can solve problems such as poor performance and receiving data errors, and achieve the effects of fast self-adaptation, accurate decoding, and avoiding receiving data errors

Active Publication Date: 2015-05-20
SHANGHAI HUAHONG INTEGRATED CIRCUIT
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  • Claims
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AI Technical Summary

Problems solved by technology

[0003] The performance of the existing asynchronous decoder of the BMC signal is not good when the received signal has glitches, and it is easy to cause errors in the received data

Method used

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  • Asynchronous decoder and asynchronous decoding method for BMC (Biphase Mark Coding) signal
  • Asynchronous decoder and asynchronous decoding method for BMC (Biphase Mark Coding) signal

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Embodiment Construction

[0019] combine figure 2 The realization principle of the asynchronous decoder of the BMC signal as shown is as follows:

[0020] A clock with a frequency much higher than the bit rate of the BMC signal is used as the sampling clock, that is, the clock signal clk, and a level counter is used to record the number of clock signals counted in the low level or high level of the BMC signal being received. At the reset point of the level counter, the level counter is cleared to 0 and then counted.

[0021] Use a register to record the number of sampling points of the half-bit width of the BMC signal (hereinafter referred to as the number of half-bit samples). Afterwards, at the decision point of each data, compare the value of the level counter with the number of half-bit samples, and if the value of the level counter is between 1.5 times and 2.5 times the number of half-bit samples, it is received If the value of the level counter is between 0.75 times and 1.5 times the number of...

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Abstract

The invention discloses an asynchronous decoder for a BMC (Biphase Mark Coding) signal. The asynchronous decoder comprises a deburring circuit, a phase jump detection circuit, a level counter, a register, an adaptive logic circuit and a judgment logic circuit, wherein the phase jump detection circuit is used for detecting the edge of the phase change of the BMC signal, and taking the edge of the phase change as a judgment point of data, a reset point of the level counter and an update point of a half-bit sample point quantity; the level counter is used for recording the sample point quantity of each level; at the judgment point of the data, a judgment on whether 0 or 1 is received is made through comparison of the size relation between the level counter and the half-bit sample point quantity; and the half-bit sample point quantity is acquired through the adaptive logic circuit. The invention further discloses an asynchronous decoding method for the BMC signal. Through adoption of the asynchronous decoder and the asynchronous decoding method, the reception performance of the asynchronous decoder for the BMC signal can be improved, and reception data errors are avoided.

Description

technical field [0001] The invention relates to an asynchronous decoder for BMC (Biphase Mark Coding) signals. The invention also relates to an asynchronous decoding method of the BMC signal. Background technique [0002] BMC signal encoding waveform such as figure 1 As shown, it belongs to a phase modulation coding method, which is a coding method that mixes clock and data for transmission; its principle is to use a clock frequency twice the transmission bit rate as a reference, and split the original bit data into Two parts, when the data is 1, the potential is changed once in the middle of the bit (1->0 or 0->1) to become 10 or 01, when the data is 0, the potential is not changed, and it becomes 11 or 00. At the same time, the level at the beginning of each bit is different from the level at the end of the previous bit, so that the receiving end can judge the boundary of each bit. The use of BMC encoding allows the transmitting end and the receiving end to transmit ...

Claims

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Application Information

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IPC IPC(8): H03M13/00
Inventor 汤晓岚
Owner SHANGHAI HUAHONG INTEGRATED CIRCUIT
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