Ultrathin semiconductor device and preparation method

Abstract

The invention aims to provide a power semiconductor device with a chip which is relatively small in size and is thinned, and a preparation method of the power semiconductor device. A platform structure is arranged at the top of each base of a chip mounting unit; the chip is inversely mounted on the chip mounting unit; the electrode on the front side of the chip is electrically connected with the base; one internal plastic package body is adopted to wrap the chip mounting unit and the chip; the top sides of the platform structures and the back side of the chip are all exposed outside the top side of the internal plastic package body; a plurality of top electrodes arranged on the top side of the internal plastic package body are respectively, correspondingly and electrically connected with different platform structures and the back side of the chip.

Description

Technical field [0001] The present invention generally relates to a semiconductor device and a manufacturing method thereof. More specifically, the present invention aims to provide a power semiconductor device with a smaller size and thinner wafer and a manufacturing method thereof. Background technique [0002] In DC-DC conversion devices, the power consumption of power devices is generally relatively large. Based on the consideration of improving the electrical performance and heat dissipation performance of the device, it is usually a part of the metal electrode of the device from the plastic packaging material that covers the chip. The center and the outside are exposed in order to obtain the best heat dissipation effect. For example, in the US patent application US2003 / 0132531A1, a semiconductor package structure 24 with exposed electrodes on the bottom of the chip and used to support surface mount technology, such as figure 1 As shown, a power chip MOSFET 10 is arranged in...

AI Technical Summary

Problems solved by technology

Although the encapsulation structure 24 solves the problem of heat dissipation to a certain extent, it is expensive to manufacture such an object as the metal can-shaped structure 12 in actual production.

On the other hand, the positions of the source contact terminal 18 and the gate contact terminal are fixed, for example, the gate contact terminal cannot be adjusted to be in the same column as the raised edge 22, so it is difficult to fit the pad layout on the PCB. matching, this package is not compatible with conventional PCB pads, which undoubtedly inhibits the scope of application of the package structure 24

In addition, the substrate resistance of chips used in power devices is usually relatively large, which leads to an increase in the on-resistance RDson of the device. In the existing wafer-level packaging technology, it is usually based on thinning the wafer There is a way to thin the chip, but this will still cause the risk of wafer cracking, so how to thin the chip to properly reduce the substrate resistance of the chip is still a problem we need to solve

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