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Interpolation estimation method in parallel demodulation bit synchronization

A technology of bit synchronization and interpolation, applied in the field of satellite data transmission, which can solve the problems that serial mode cannot meet the requirements, signal symbol rate is high, and clock frequency is low.

Inactive Publication Date: 2015-06-17
WUHAN UNIV
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Problems solved by technology

Commonly used digital processors (such as FPGA) can work stably at a relatively low clock frequency, but with the development of communication technology, the amount of data to be processed has increased sharply, and the signal symbol rate has become higher and higher, and the serial method has gradually been unable to meet the requirements. Require

Method used

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  • Interpolation estimation method in parallel demodulation bit synchronization
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Embodiment

[0074] The invention is based on an all-digital bit synchronization algorithm in which an analog input signal x(t) with a symbol rate T is processed by a local fixed clock period T s After sampling, it becomes a discrete signal x(mT s ). The value obtained by the interpolation filter is sent to the timing error detector to obtain the error τ(n) between the input signal and the local clock, and then a loop filter is used to filter out the noise and high-frequency components, and the obtained value e (n) sent to the controller to calculate the integer sampling time m k and interpolation filter interpolation point position u k , so as to obtain the timing output y(kT i ); the specific method is as follows:

[0075] 1. Derivation of the relationship between η(N(m+1)) and η(Nm), W(Nm) in parallel mode.

[0076] A. In parallel mode, we assume that there are N signals, then the data rate becomes 1 / NT s .

[0077] B. Sampling period T s and the symbol period T ratio,

[007...

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Abstract

The invention belongs to the field of satellite data transmission and particularly relates to an interpolation estimation method in parallel demodulation bit synchronization. According to the scheme, data sampled by a receiver are parallelized, the processing speed in an FPGA is reduced, and the problems related to the design of an NOC and computation of an interpolation moment in parallel demodulation bit synchronization are solved. The interpolation estimation method has the uppermost advantage that deceleration can be conducted on high-speed data collected by the receiver so that the corresponding demodulation process can be achieved in the FPGA.

Description

technical field [0001] The invention belongs to the field of satellite data transmission, in particular to an interpolation estimation method in parallel demodulation and bit synchronization. Background technique [0002] With the rapid development of satellite communication technology, the amount of data to be processed has increased sharply, and the requirements for real-time transmission between satellites and the ground have become higher and higher, making the ground receiving system tend to develop high-speed bandwidth digital processing. In high-speed digital communication systems, The symbol rate is generally hundreds of megabytes. After AD sampling, the data rate of the sampled signal is even higher. Data transmission system is an important part of satellite payload, and modulation and demodulation technology is one of the core technologies in satellite data transmission system, and it is also the bottleneck restricting the research of high-speed data transmission s...

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Application Information

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IPC IPC(8): H04L7/00H04B7/185
Inventor 罗义军李劲李勤谢左雷张享
Owner WUHAN UNIV
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