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Power-failure protection method of nonvolatile memory and device thereof

A non-volatile, power-down protection technology, applied in static memory, read-only memory, information storage, etc., can solve the problem of inaccurate data read by the storage unit

Active Publication Date: 2015-07-01
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides a power-down protection method and device for a non-volatile memory to solve the problem of reading memory cells due to over-erasing phenomenon after power-on when abnormal power-off occurs during the erasing operation. The problem of inaccurate data

Method used

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  • Power-failure protection method of nonvolatile memory and device thereof
  • Power-failure protection method of nonvolatile memory and device thereof
  • Power-failure protection method of nonvolatile memory and device thereof

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Experimental program
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Embodiment 1

[0062] refer to Figure 4 , which shows a flow chart of a non-volatile memory power-down protection method according to Embodiment 1 of the present invention, and the method may specifically include the following steps:

[0063] Step 401, recording erasing information when power is off.

[0064] In the embodiment of the present invention, the power-off may refer to at the same time as the power-off (that is, during the power-off process). If the non-volatile memory is powered down, erasure information can be recorded during the power down process. Wherein, the recorded erasing information can be used as a basis for subsequently judging whether abnormal power failure occurs during the erasing operation. The non-volatile memory in the embodiment of the present invention may be flash memory, EEPROM, and the like.

[0065] Step 402, when the power is turned on again after the power failure, it is judged according to the erasing information whether abnormal power failure occurs ...

Embodiment 2

[0071] refer to Figure 5 , which shows a flow chart of a method for power-down protection of a non-volatile memory according to Embodiment 2 of the present invention, and the method may specifically include the following steps:

[0072] Step 501, recording erasing information when power is off.

[0073] The purpose of the embodiments of the present invention is mainly to judge whether an abnormal power-off occurs during the execution of the erase operation according to the recorded erasing information after the non-volatile memory is powered on, and if an abnormal power-off occurs, then according to the erase information Erase verification is performed on deleted information. Therefore, in the embodiment of the present invention, when the non-volatile memory is powered off, erasure information can be recorded. delete information.

[0074] In a preferred embodiment of the present invention, a power-down protection area may be separately set in the non-volatile memory for re...

Embodiment 3

[0110] refer to Figure 8 , which shows a structural block diagram of a non-volatile memory power-down protection device according to Embodiment 3 of the present invention. The device may specifically include the following modules:

[0111] The first recording module 801 is used for recording erasing information when power is off;

[0112] Judging module 802, configured to judge whether an abnormal power-off occurs during the erasing operation according to the erasing information when the power is turned on again after power-off;

[0113] The verification module 803 is configured to perform over-erasure verification according to the erasure information when the judging result of the judging module is that an abnormal power failure has occurred.

[0114] In a preferred embodiment of the present invention, the erasing information may be recorded in a preset power-down protection area, and the erasing information may include a power-down flag and an address of the erasing area. ...

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Abstract

The invention provides a power-failure protection method of a nonvolatile memory and a device thereof. When abnormal power failure happens during erase operation, data read from a memory cell is not accurate due to over-erase after power-on again. The above problem can be solved by the method and the device in the invention. The method comprises the following processes: during power failure, erase information is recorded; during power-on again after power failure, whether abnormal power failure happens during the erase operation is judged according to the erase information; and if abnormal power failure happens, over-erase checkout is carried out according to the erase information. According to the invention, reliability of data read from the memory cell after power-on again can be guaranteed if abnormal power failure happens during the erase operation of the nonvolatile memory.

Description

technical field [0001] The invention relates to the technical field of semiconductor memory, in particular to a power-down protection method and device for a non-volatile memory. Background technique [0002] Non-volatile memory refers to a memory that can still retain data after power failure, that is, the stored data will not be lost after power failure. Flash Memory (Flash Memory) and EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) are both non-volatile memories. [0003] Such as figure 1 Shown is a schematic structural diagram of a non-volatile memory. The non-volatile memory includes a physical block (physical BLOCK), and a physical block includes a plurality of storage units (cells), a plurality of bit lines (bit lines, BL), and a plurality of word lines (word lines, WL), figure 1 Among them, MN1, MN2, MN3, MN4... are memory cells, BL1, BL2, BL3, BL4... are bit lines, WL1, WL2, WL3, WL4... That is th...

Claims

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Application Information

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IPC IPC(8): G11C16/14
Inventor 王林凯胡洪洪杰
Owner GIGADEVICE SEMICON (BEIJING) INC