Formation method of sram unit

Abstract

A method for forming an SRAM unit, comprising: forming: first, second, third, fourth, fifth, and sixth fins; a first grid across the first, second, and third fins; across the first, second The second gate of the fin, the first and second fins between the first and second gates are the first drain; the third gate across the fourth, fifth and sixth fins is across the fifth, The fourth gate of six fins, the fifth and sixth fins between the third and fourth gates are the second drain; the fifth source and third drain of the third fins on both sides of the first gate ; the sixth source and the fourth drain of the fourth fin on both sides of the third gate; forming an interlayer dielectric layer; the first patterning forms a first trench, across the first and second fins of the first drain part, the third fin of the third drain; the second patterning forms a second trench, across the fifth and sixth fins of the second drain, and the fourth fin of the fourth drain; in the first trench The groove forms the first metal layer, and the second groove forms the second metal layer. SRAM cells are realized technologically.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an SRAM unit. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] A static random access memory includes a plurality of static random access memory units (hereinafter referred to as SRAM units), the plurality of SRAM units are arranged in an array, and a SRAM unit includes six transistors (6-T). As the integration level of integrated circuits increases, the feature size of SRAM cells gradually decreases and the wafer area occupied by them becomes smaller and smaller. Compared with the size of the planar MOS transistor, the size of the fin field effect transistor is smal...

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Problems solved by technology

[0012] The problem solved by the present invention is that the signal transmission speed of the existing SRAM unit comprising six fin field effect transistors is low and the performance is not good

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