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Multi-core processor system, interrupt routine and interrupt method

A multi-core processor, interrupt signal technology, used in multi-programming devices, program synchronization, resource allocation, etc.

Inactive Publication Date: 2015-07-22
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the core does not operate in the slave CPU, and only has the minimum necessary thread execution program and interrupt control function from the master CPU, thereby minimizing the overhead of the OS-based kernel

Method used

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  • Multi-core processor system, interrupt routine and interrupt method
  • Multi-core processor system, interrupt routine and interrupt method
  • Multi-core processor system, interrupt routine and interrupt method

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Embodiment Construction

[0026] Embodiments of the multi-core processor system, interrupt program, and interrupt method involved in the present invention will be described in detail below with reference to the accompanying drawings. In addition, in the multi-core processor system of this embodiment, a so-called multi-core processor is a processor equipped with a plurality of cores. As long as a plurality of cores are installed, it may be a single processor equipped with a plurality of cores, or a processor group in which single-core processors are arranged. In addition, in this embodiment, in order to simplify the description, a processor group in which single-core processors are arranged is used as an example for description.

[0027] (Hardware configuration of multi-core processor system)

[0028] figure 1 It is a block diagram showing the hardware configuration of the multi-core processor system according to this embodiment. exist figure 1 Among them, the multi-core processor system 100 is comp...

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Abstract

The invention relates to a multi-core processor system, an interrupt routine and an interrupt method. When an exclusive starting event is detected in an application (A), an interrupt signal (the exclusion starts) is informed to a thread (B). When the information of the exclusive starting event is received, a slave CPU (102) is released through the evading of the thread (B). Since a thread (Y) exists in a thread queue, the thread (Y) is allocated to the slave CPU (102). Accordingly, the thread (Y) is executed in the slave CPU (102). When the thread (Y) is finished, the thread queue is empty, and therefore the mode is transferred to a low-power mode. Then, when an exclusive finishing event is detected in the application (A), an interrupt signal (the exclusion is finished) is informed to the slave CPU (102) form the application (A). In the slave CPU (102), when the information of the exclusive finishing event is received, the thread (B) is restored in the slave CPU (102). Therefore, the execution can be performed again from the position where the thread (B) is allocated.

Description

[0001] This divisional application is a divisional application of an invention patent application with application number 201080063240.6 and an application date of February 23, 2010. The invention title of the invention patent application is "multi-core processor system, interrupt program, and interrupt method". technical field [0002] The present invention relates to a multi-core processor system, an interrupt program, and an interrupt method for controlling thread interrupt. Background technique [0003] Multi-core processor systems have been disclosed in the past. For example, there is a multi-core processor system in which a core of an OS (Operating System, operating system) is not activated in a slave CPU (Central Processing Unit), but a slave library (slave library) to start a thread (for example, refer to the following patent documents 1 to 4.). In this case, the slave CPU does not operate the core, but only has a minimum necessary thread execution program and an in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F9/46G06F9/52
Inventor 山下浩一郎山内宏真宫崎清志
Owner FUJITSU LTD
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