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Process for fabricating a semiconductor-on-insulator substrate

一种制造方法、半导体的技术，应用在半导体/固态器件制造、电气元件、电路等方向，能够解决长热处理时间等问题，达到减小表面粗糙度的效果

Inactive Publication Date: 2015-07-22
SOITEC SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, considering the relatively long heat treatment times and for economical reasons, it is not impossible from an industrial point of view to implement such a method in an oven 10 comprising only a single structure 20

Method used

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  • Process for fabricating a semiconductor-on-insulator substrate
  • Process for fabricating a semiconductor-on-insulator substrate
  • Process for fabricating a semiconductor-on-insulator substrate

Examples

Experimental program
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Effect test

Embodiment 1

[0075] The heat treatment according to the invention is carried out on a silicon-on-insulator structure 200 comprising a silicon dioxide layer with a thickness of 30 to 40 nm and a semiconductor layer made of silicon with a thickness of 100 nm.

[0076] The heat treatment is performed at a temperature of 1200° C. for 5 to 10 minutes in a non-oxidizing atmosphere including only argon and nitrogen. This heat treatment allows the thickness of the silicon dioxide layer to be reduced to between 10 and 20 nm.

[0077] After the heat treatment, the structure 200 is subjected to a step of thinning the silicon layer, ie oxidation followed by oxygen removal, in order to obtain a silicon layer 12 nm thick.

[0078] During the heat treatment, if the pressure of the non-oxidizing atmosphere is equal to 1 bar, this results in a silicon dioxide layer with a thickness non-uniformity of 3 nm and a silicon layer with a thickness non-uniformity of 1.5 nm.

[0079] Reducing the pressure of the n...

Embodiment 2

[0081] The heat treatment according to the invention is carried out on a silicon-on-insulator structure 200 comprising a silicon dioxide layer with a thickness of 30 to 40 nm and a semiconductor layer made of silicon with a thickness of 300 nm.

[0082] The heat treatment is performed at a temperature of 1200° C. for about ten hours in a non-oxidizing atmosphere including only argon and nitrogen. This heat treatment allows the thickness of the silicon dioxide layer to be reduced to between 10 and 20 nm.

[0083] After the heat treatment, the structure 200 is subjected to a step of thinning the silicon layer, ie oxidation followed by oxygen removal, in order to obtain a silicon layer 12 nm thick.

[0084] During the heat treatment, if the pressure of the non-oxidizing atmosphere is equal to 1 bar, this results in a silicon dioxide layer with a thickness non-uniformity of 1 to 1.5 nm and a silicon layer with a thickness non-uniformity of 0.5 to 1 nm.

[0085] Reducing the press...

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PUM

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Abstract

The present invention relates to a process for fabricating a plurality of semiconductor-on-insulator structures (200), said insulator being a layer (202) of silicon dioxide having a thickness smaller than 50 nm, each structure (200) comprising a semiconductor layer (203) placed on the silicon- dioxide layer (202), said fabrication process comprising a step of heat treating the plurality of structures (200), which heat treatment step is designed to partially dissolve the silicon-dioxide layer (202), the heat treatment step being carried out in a non-oxidising atmosphere and the pressure of said non-oxidising atmosphere being lower than 0.1 bar.

Description

technical field [0001] The present invention relates to the field of manufacturing semiconductor-on-insulator substrates. Background technique [0002] A known prior art fabrication method as shown in FIGS. 1A and 1B is a method of fabricating a plurality of semiconductor-on-insulator structures 20, the insulator being a silicon dioxide layer 22 with a thickness of less than 50 nm, comprising multiple Each structure 20 is subjected to a heat treatment step designed to partially decompose the silicon dioxide layer 22 . [0003] In this regard, those skilled in the art will find a technical description of the decomposition of silicon dioxide layers in the following article by Kononchuck: Kononchuck et al., Novel trends in SOI technology for CMOS applications, Solid state Phenomena, vol. 156-158 (2010) pp. 69-76; and Kononchuck et al., Internal Dissolution of Buried Oxide in SOI Wafers, Solid State Phenomena, Vol. 131-133 (2008) pp. 113-118. [0004] Each structure 20 compris...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762
CPCH01L21/76251H01L21/324H01L21/7624H01L21/84
Inventor C·古德尔奥列格·科农丘克
Owner SOITEC SA
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