Control logic circuit with low fan-in

Abstract

The invention discloses a control logic circuit with low fan-in. The control logic circuit is characterized in that the control logic circuit comprises a main control logic trigger circuit, a main control logic circuit and a sub control logic circuit; the main control logic trigger circuit is used for generating a triggering signal driving the main control logic circuit to work; the main control logic circuit is used for generating input of the sub control logic circuit and comprises an and gate and four same dynamic logic units; the dynamic logic units are used for dividing 16 comparison results of a comparator into four groups and latching the four groups in order; each sub control logic circuit comprises four NOR gates and 16 same dynamic logic units, and the dynamic logic units are used for latching and outputting 16 latching results of the main control logic circuit. The beneficial effects of the control logic circuit with low fan-in are that the control logic circuit has low fan-in in the premise of meeting low-latching time, fan-out of a comparator is lowered, and thus the comparator can work in a high speed.

Description

technical field [0001] The invention relates to a control logic circuit, in particular to a control logic circuit with low fan-in, and belongs to the field of analog integrated circuits. Background technique [0002] SAR ADC (Successive Approximation Analog-to-Digital Converter) has become a research hotspot in the industry and academia in recent years due to its advantages such as simple structure, low power consumption, easy integration, and small area. The design of a high-speed SAR ADC is mainly limited by the speed of the comparator and the settling time of the DAC network. With the improvement of the precision of SAR ADC, the load capacitance of the comparator will increase a lot when the traditional control logic circuit is adopted, which makes the design of the high-speed comparator more difficult. If the number of dynamic logic units in the control logic part can be reduced to reduce the load capacitance of the comparator, the speed of the comparator will be greatl...

AI Technical Summary

Problems solved by technology

The design of a high-speed SAR ADC is mainly limited by the speed of the comparator and the settling time of the DAC network

With the improvement of the accuracy of SAR ADC, the load capacitance of the comparator will increase a lot when using the traditional control logic circuit, which makes the design of high-speed comparator more difficult

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