Control logic with low fan-in

Abstract

The invention discloses a control logic circuit with low fan-in, which is characterized in that it comprises: a main control logic trigger circuit, a main control logic circuit and a sub-control logic circuit, and the main control logic trigger circuit is used to generate the main control logic The trigger signal of the circuit work; the main control logic circuit is used to generate the input of the sub-control logic circuit, which includes 1 AND gate and 4 identical dynamic logic units, which are used to compare 16 comparators The results are divided into 4 groups and sequentially latched; the sub-control logic circuit includes 4 NOR gates and 16 identical dynamic logic units, which are used to latch the 16 latch results of the main control logic circuit respectively output. The invention is beneficial in that: under the premise of satisfying the low latch time, it has lower fan-in, reduces the fan-out of the comparator, and enables the comparator to work at a faster speed.

Description

technical field [0001] The invention relates to a control logic circuit, in particular to a control logic circuit with low fan-in, and belongs to the field of analog integrated circuits. Background technique [0002] SAR ADC (Successive Approximation Analog-to-Digital Converter) has become a research hotspot in the industry and academia in recent years due to its advantages such as simple structure, low power consumption, easy integration, and small area. The design of a high-speed SAR ADC is mainly limited by the speed of the comparator and the settling time of the DAC network. With the improvement of the precision of SAR ADC, the load capacitance of the comparator will increase a lot when the traditional control logic circuit is adopted, which makes the design of the high-speed comparator more difficult. If the number of dynamic logic units in the control logic part can be reduced to reduce the load capacitance of the comparator, the speed of the comparator will be greatl...

AI Technical Summary

Problems solved by technology

The design of a high-speed SAR ADC is mainly limited by the speed of the comparator and the settling time of the DAC network

With the improvement of the accuracy of SAR ADC, the load capacitance of the comparator will increase a lot when using the traditional control logic circuit, which makes the design of high-speed comparator more difficult

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