Electrostatic discharge protection circuit

Abstract

The invention relates to the technical field of circuit and electronics, and concretely relates to an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes a trigger module, a current generation unit and an SCR module. When a VDD has a positive ESD pulse, an RC coupling effect enables a grid electrode of a first NMOS transistor to be in high level, a first current passing across the VDD, a first PMOS transistor, the first NMOS transistor and a GND is generated, a second PMOS transistor is conducted, a second current is generated, an NPN tripolar transistor is turned on, the current of a collector electrode of the NPN tripolar transistor passes across a first resistor to enable an emitter-base electrode of a PNP tripolar transistor to be positively biased, the PNP tripolar transistor is turned on, and the positive feedback effect enables an SCR formed by the PNP tripolar transistor and the NPN tripolar transistor to start discharge. According to the technical scheme, the trigger voltage is low, the response speed is fast, and the circuit, with only a small dimension, has the excellent ESD protection performance.

Description

technical field [0001] The invention relates to the technical field of circuit electronics, in particular to an electrostatic protection circuit. Background technique [0002] The problem of Electrostaticdischarge (ESD) becomes more and more serious in IC products as the nodes get smaller. Commonly used ESD protection devices include MOS, DIODE, and SCR. Among them, SCR unit size has the strongest ESD protection ability. figure 1 It is a commonly used NMOS-based ESD protection structure. Using the characteristics of RC coupling, when there is a positive ESD pulse on VDD, the RC coupling effect makes the gate of the last NMOS high, and the NMOS starts to discharge. The disadvantage is that the discharge capacity per unit size of NMOS is relatively poor, and this circuit design requires a very large discharge NMOS transistor. Due to the large size of the NMOS, a three-stage inverter structure is required in the front stage to ensure that the NMOS can be turned on and disch...

AI Technical Summary

Problems solved by technology

The reverse breakdown voltage of N+ / PW is much lower than that of NW / PW, which makes the trigger voltage of LVTSCR lower than that of traditional SCR

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