Method for controlling memory chip, chip controller and memory controller

Abstract

A method for controlling a memory chip, a chip controller, and a memory controller. The chip controller (200) comprises: a registering module (210), used for registering independent chip selection information; a control module (220), used for receiving a first chip selection signal output by the memory controller (110); generating multiple independent chip selection signals according to the first chip selection signal and the independent chip selection information registered by the registering module (210), wherein the multiple independent chip selection signals are in one-to-one correspondence with multiple memory chips (122), the first chip selection signal is used for instructing selection of the multiple memory chips, and the independent chip selection information is used for instructing independent selection of at least one of the multiple memory chips; and outputting the multiple independent chip selection signals to the multiple memory chips respectively, so that the at least one of the multiple memory chips performs, according to a control command signal output by the memory controller, an operation corresponding to the control command signal. The present invention can effectively reduce occupation of the transmission bandwidth of a DRAM system.

Description

technical field [0001] The embodiments of the present invention relate to the computer field, and in particular to a method for controlling a memory chip, a chip controller and a memory controller. Background technique [0002] The computer architecture has a memory system, and the most commonly used storage medium for the memory system is Dynamic Random Access Memory (DRAM). The memory of the computer is often in the form of Dual Inline Memory Modules (DIMMs), and registerable DIMMs (Registered DIMMs, RDIMMs) and low-load DIMMs (Load-Reduced DIMMs, LRDIMMs) are two commonly used DIMM form. RDIMM and LRDIMM receive address signal, chip select signal and clock enable signal from the memory controller, and output to each DRAM chip on the DIMM after being registered by the register module. [0003] The working principle of a common RDIMM is as follows: a plurality of narrow-bit-width DRAM chips form a wide-bit-width DIMM. RDIMM has a circuit or chip with a registration funct...

AI Technical Summary

Problems solved by technology

[0005] However, each DRAM command of the memory controller needs to send a separate chip selection information in the previous cycle of the DRAM command, which seriously occupies the transmission bandwidth of the DRAM system.

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