Phase Locked Loop System

Abstract

The present invention provides a phase-locked loop system, wherein the phase-locked loop system at least includes: a delay unit for delaying a reference clock signal and a feedback clock signal; a phase-locked loop component connected to the delay unit for The delayed reference clock signal and the feedback clock signal output a first signal locked to the frequency and phase of the reference clock signal. The present invention superimposes the delay unit into the phase-locked loop component, and by delaying the reference clock signal and the feedback clock signal, reverse digitally compensates the phase difference between the reference clock signal and the feedback clock signal to eliminate the reference clock signal and the feedback clock signal The skew will not affect the performance of the phase-locked loop components themselves; by adjusting the delay accuracy of the reference clock signal and the feedback clock signal, to achieve fine adjustment of the phase difference locked by the original phase-locked loop, so that in On the premise of ensuring the performance of the phase-locked loop components, phase locking in the order of 10 ps to 20 ps can be realized.

Description

technical field [0001] The invention relates to a phase-locked loop, in particular to a phase-locked loop system with a digital compensation function capable of eliminating clock skew. Background technique [0002] The clock in the SoC system (System on Chip, system on chip) usually needs to generate a series of clocks that are not skewed with the clock source for the subsequent system. However, skew (skew) will inevitably occur during the clock transmission process. ), at this time the SoC system usually requires this skew to be limited to a smaller index, so as to ensure that the sampling module in the subsequent system has sufficient design margin. As the system clock frequency increases gradually, the requirement for this skew index becomes higher and higher. [0003] A traditional deskew PLL (deskew Phase Locking Loop), like a clock generator PLL, can generate an output clock that is phase-locked to a reference clock. However, unlike the clock generator PLL, the feedb...

AI Technical Summary

Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a phase-locked loop system for solving the problem that the traditional anti-skew phase-locked loop in the prior art can only bring limited gain, and the limited The clock skew of the gain elimination cannot meet the requirements of the index, which causes the problem of deterioration of the skew index of the anti-skew PLL, or the traditional anti-skew PLL reduces the clock skew by reducing the current of the charge pump , which in turn causes the problem that the noise contribution of the charge pump deteriorates

Images