Universal verification platform and method for development of network core chip technology

Abstract

The invention discloses a universal verification platform and method for development of network core chip technology, and relates to the field of the network core chip technology. The platform comprises a power module, a CPU module, an FPGA module, a clock module, a PLL module, a DDS module, a cross module, an FPGA module, a backboard signal connector, an optical module and a RJ45 connector; the CPU module is connected with the FPGA module through the clock module, the PLL module, the DDS module and the cross module respectively; the FPGA module is connected with the RJ45 connector; and the cross module is respectively connected with the backboard signal connector and the optical module. The optical module comprises an SFP optical module connector and an XFP optical module connector; the backboard signal connector comprises a compatible high speed connector and a compatible low speed connector; and the RJ45 connector comprises two RJ45 interfaces. The universal verification platform disclosed by the invention can be used for verifying a variety of chips, so that the use cost is lower, and the resource utilization is quite reasonable.

Description

technical field [0001] The invention relates to the technical field of network core chips, in particular to a general verification platform and method for the development of network core chip technology. Background technique [0002] With the advancement of communication technology, the services carried by the communication network have undergone tremendous changes, and various new technologies have emerged one after another. For the optical transport network, the main optical transport network technologies are generally OTN (Optical Transport Network, optical transport network) and PTN (Packet Transport Network, packet transport network); for the optical access network, the mainstream access method is generally It is XG-PON (X-Gigabit-CapablePON, 10 gigabit passive optical network) and 10G-EPON (passive optical network of 10 Gigabit Ethernet). [0003] At present, mainstream operators and manufacturers at home and abroad are very concerned about the development and applica...

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Problems solved by technology

[0005] At present, when operators design a verification platform, they can only design a verification platform for a certain type of chip. Because the materials for a verification platform required for the verification of new technologies are relatively expensive, the development also requires more manpower and time costs. , so the cost of designing a verification platform for a class of chips is relatively high, and the resource utilization is not reasonable enough

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