Coarse-grained parallel routing method for fpga based on optimal division of netlist location information

Abstract

The invention discloses a method for FPGA coarse-grained parallel wiring based on optimal division of netlist position information. Through a recursive method, task division is implemented, and the wiring information of tasks can be synchronized, so that the wiring paths of all signal lines can be searched based on the current punishment cost; aiming at a wiring set N, a serial wiring method is adopted if the set is small enough; N is divided into sets S-, S0 and S+ which are respectively a signal line set S0 crossing two sub regions, a signal line set S- at left (lower) sub region and a signal line set S+ at the right (upper) sub region if the set does not meet the small enough condition; S- and S+ are respectively subjected to task division along different directions by a recursive division method, so that a signal line set in a binary tree form can be generated; the parallel wiring operation is implemented, so that the wiring process is completed. According to the method, the FPGA developing efficiency is improved, the work time and work cost are saved, and the wide application of FPGA can be promoted.

Description

technical field [0001] The invention belongs to the field of electronic design automation, and relates to an electronic design automation wiring method, in particular to an FPGA coarse-grained parallel wiring method based on optimal division of netlist position information. Background technique [0002] As the scale of field programmable gate array (FPGA) continues to increase significantly, the corresponding electronic design automation (electrical design automatic, EDA) tools need to spend a lot of running time to comprehensively process these large-scale circuits. design. At present, it is hoped to alleviate this problem from two perspectives: one is to use the modularization, hierarchy and design reuse of engineering design methodology; Challenges posed by prolonged periods of time. [0003] Layout is one of the longest steps in the overall EDA design flow. The overall process of wiring is as follows figure 1 As shown in Fig. 1, the layout design is carried out first...

AI Technical Summary

Problems solved by technology

[0004] The existing method relies on disconnecting and reconnecting serial wiring work, which is very time-consuming, and as the FPGA density increases, it will take up more time, thereby affecting engineering productivity, increasing work costs, and affecting Widespread use of FPGAs by software developers creates certain barriers

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