Eureka AIR delivers breakthrough ideas for toughest innovation challenges, trusted by R&D personnel around the world.

SHA256 realizing method and system based on large-scale coarse-grain reconfigurable processor

A processor and coarse-grained technology, applied in the architecture with a single central processing unit, electrical digital data processing, instruments, etc., can solve the problems of low computing efficiency and speed, improve computing parallelism, reduce computing cycles, improve The effect of computing efficiency

Active Publication Date: 2016-02-17
SOUTHEAST UNIV
View PDF4 Cites 19 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the interconnection of these arrays is relatively simple, and the operation of the SHA256 method requires a large amount of intermediate data storage and a large number of rounds, so the efficiency and speed of the operation are low
Traditional reconfigurable computing systems have big problems in terms of computing efficiency and computing cycles of SHA256

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • SHA256 realizing method and system based on large-scale coarse-grain reconfigurable processor
  • SHA256 realizing method and system based on large-scale coarse-grain reconfigurable processor
  • SHA256 realizing method and system based on large-scale coarse-grain reconfigurable processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] The present invention will be further described below in conjunction with the accompanying drawings.

[0034] figure 1 It is a structural block diagram based on a large-scale coarse-grained reconfigurable processor, which includes 10 reconfigurable array blocks, 1 general-purpose register file, 1 input FIFO register bank and 1 output FIFO register bank. Data transfers between the reconfigurable processor and the bus interface are buffered by a first-in first-out register bank. The general register file is used for data communication and data cache between reconfigurable array blocks.

[0035] The reconfigurable array block further includes 4 reconfigurable array operation rows, a general register file read port operation row selector and a general register file write port operation row selector. Through a general-purpose register read port operation line selector, you can choose to read the data of the general-purpose register file from the specified reconfigurable ar...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an SHA256 realizing method and system based on a large-scale coarse-grain reconfigurable processor. The system comprises a first-in first-out register set, a general register file, an arithmetic logic unit, a bit permutation network, a byte permutation network, a data loading unit and a data output unit. Aiming at an SHA256 method, by means of multiple times of iteration, optimization and acceleration are carried out in the reconfigurable processor in a partial expansion and middle result data caching mode.

Description

technical field [0001] The invention designs the field of embedded reconfigurable systems, especially a large-scale coarse-grained embedded reconfigurable system and its processing method applied in the fields of communication and encryption. Background technique [0002] General-purpose processors and application-specific integrated circuits (ASICs) are two mainstream methods in the field of traditional computer system architecture. However, with the increasing demand for system performance, energy consumption, time-to-market and other indicators in the application field, the disadvantages of these two traditional computing models are exposed. [0003] The general-purpose processor method has a wide range of applications, but the calculation efficiency is low. Although the application-specific integrated circuit can improve the calculation speed and calculation efficiency and meet the performance requirements, the flexibility of the ASIC device is very poor. [0004] In or...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78
CPCG06F15/7867
Inventor 曹鹏陈圣华杨锦江陆启乐刘波
Owner SOUTHEAST UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com