Shift register, grid drive circuit and display device
A technology for shift registers and gates, which is applied in the field of gate drive circuits, display devices, and shift registers, and can solve problems such as weak discharge capability of switching transistors, large scanning signal noise, and reduced voltage of pull-down nodes.
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Embodiment 1
[0125] by Figure 5b The structure of the shift register shown is taken as an example to describe its working process, wherein, in Figure 5b In the shift register shown, all the switch transistors are N-type switch transistors, and each N-type switch transistor is turned on under the action of a high potential, and is turned off under the action of a low potential; the potential of the reference signal terminal VSS is a low potential, and the corresponding The input and output timing diagram is as follows Figure 7a Shown, specifically, select as Figure 7a There are five stages in the shown input-output timing diagram, the first stage T1 , the second stage T2 , the third stage T3 , the fourth stage T4 and the fifth stage T5 .
[0126] In the first phase T1, Input=1, Reset=0, CK1=1, CK2=0.
[0127] Since Reset=0, both the second switch transistor M2 and the thirteenth switch transistor M13 are turned off; because Input=1, the first switch transistor M1 is turned on; becaus...
Embodiment 2
[0139] by Figure 6b The structure of the shift register shown is taken as an example to describe its working process, wherein, in Figure 6b In the shift register shown, all the switching transistors are P-type switching transistors, and each P-type switching transistor is turned on under the action of a low potential, and is turned off under the action of a high potential; the potential of the reference signal terminal VSS is a high potential, and the corresponding The input and output timing diagram is as follows Figure 7b Shown, specifically, select as Figure 7b There are five stages in the shown input-output timing diagram, the first stage T1 , the second stage T2 , the third stage T3 , the fourth stage T4 and the fifth stage T5 .
[0140] In the first phase T1, Input=0, Reset=1, CK1=0, CK2=1.
[0141] Since Reset=1, both the second switch transistor M2 and the thirteenth switch transistor M13 are turned off; because Input=0, the first switch transistor M1 is turned ...
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