FPGA-based binary synchronization communication protocol controller

A protocol controller and synchronous communication technology, applied in the field of data communication, can solve the problems of inconvenient porting across processor platforms, difficulty in realizing multi-channel implementation, etc.

Active Publication Date: 2016-04-20
THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The inventive technology is implemented on a general-purpose microprocessor using a software programming method, which is closely related to the processor i

Method used

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  • FPGA-based binary synchronization communication protocol controller
  • FPGA-based binary synchronization communication protocol controller
  • FPGA-based binary synchronization communication protocol controller

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] The specific embodiments of the present invention will be described in detail below in conjunction with tables and drawings, but the protection scope of the present invention is not limited to the embodiments.

[0046] Table 1 shows the typical control characters of the binary synchronous communication protocol.

[0047] Table 1 Typical control characters of binary synchronous communication protocol

[0048] control character

ASCII code

Function

ACK 0

DLE and 0

Acknowledge that even frames have been received intact or are ready to receive

ACK 1

DLE and 1

Acknowledgment that odd frames have been received

DLE

DLE

Data transparency sign

SYN

SYN

Synchronization flag, inform the receiver that there is a data frame coming

SOH

SOH

header information start

STX

STX

body text begins

ETB

ETB

end of text block in body

[0049] ETX

ETX

end ...

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Abstract

The invention discloses an FPGA-based binary synchronization communication protocol controller comprising a processor interface module, a data sending cache module, a data receiving cache module, a sending channel module, a receiving channel module and a baud rate generation module. The data sending cache module, the data receiving cache module, and the baud rate generation module are connected to the processor interface module; the sending channel module is connected with the data sending cache module; and the receiving channel module is connected with the data receiving cache module. The sending channel module and the receiving channel module carry out state indication interaction.

Description

technical field [0001] The invention belongs to the field of data communication, in particular to a binary synchronous communication (Binary Synchronous Communication, BSC for short) protocol controller based on FPGA (Field-Programmable Gate Array, Field Programmable Gate Array). Background technique [0002] Although with the continuous development of the information system to the network, various types of equipment and equipment connected to the information system are also developing in the direction of the network, but in order to protect the existing investment and be compatible with the previous construction system, some information system equipment Not only the high-speed primary network communication interface is configured, but also the low-speed standby serial data communication interface is reserved. Typical communication protocols supported by these low-speed standby serial communication interfaces include character-oriented synchronous communication protocols and...

Claims

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Application Information

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IPC IPC(8): H04L12/40H04L12/403H04L1/00
CPCH04L1/004H04L1/0073H04L1/0083H04L12/40058H04L12/403
Inventor 邹庆华吴刚曹伟张月雷何纬
Owner THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
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