Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A binary synchronous communication protocol controller based on fpga

A protocol controller and synchronous communication technology, applied in the field of data communication, can solve problems such as difficulty in realizing multi-channel implementation and inconvenient porting across processor platforms.

Active Publication Date: 2018-09-21
THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The inventive technology is implemented on a general-purpose microprocessor using a software programming method, which is closely related to the processor instruction set and performance, and it is inconvenient to transplant across processor platforms, and it is difficult to realize multi-channel implementation

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A binary synchronous communication protocol controller based on fpga
  • A binary synchronous communication protocol controller based on fpga
  • A binary synchronous communication protocol controller based on fpga

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0045] The specific embodiments of the present invention will be described in detail below in conjunction with tables and drawings, but the protection scope of the present invention is not limited to the embodiments.

[0046] Table 1 shows the typical control characters of the binary synchronous communication protocol.

[0047] Table 1 Typical control characters of binary synchronous communication protocol

[0048] control character

ASCII code

Features

ACK 0

DLE and 0

Acknowledge that even frames have been received intact or are ready to receive

ACK 1

DLE and 1

Acknowledgment that odd frames have been received

DLE

DLE

Data transparency sign

SYN

SYN

Synchronization flag, inform the receiver that there is a data frame coming

SOH

SOH

header information start

STX

STX

body text begins

ETB

ETB

end of text block in body

[0049] ETX

ETX

end o...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an FPGA-based binary synchronization communication protocol controller comprising a processor interface module, a data sending cache module, a data receiving cache module, a sending channel module, a receiving channel module and a baud rate generation module. The data sending cache module, the data receiving cache module, and the baud rate generation module are connected to the processor interface module; the sending channel module is connected with the data sending cache module; and the receiving channel module is connected with the data receiving cache module. The sending channel module and the receiving channel module carry out state indication interaction.

Description

technical field [0001] The invention belongs to the field of data communication, and in particular relates to a binary synchronous communication (Binary Synchronous Communication, BSC for short) protocol controller based on FPGA (Field-Programmable Gate Array, Field Programmable Gate Array). Background technique [0002] Although with the continuous development of the information system to the network, various types of equipment and equipment connected to the information system are also developing in the direction of the network, but in order to protect the existing investment and be compatible with the previous construction system, some information system equipment Not only the high-speed primary network communication interface is configured, but also the low-speed standby serial data communication interface is reserved. Typical communication protocols supported by these low-speed standby serial communication interfaces include character-oriented synchronous communication p...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/40H04L12/403H04L1/00
CPCH04L1/004H04L1/0073H04L1/0083H04L12/40058H04L12/403
Inventor 邹庆华吴刚曹伟张月雷何纬
Owner THE 28TH RES INST OF CHINA ELECTRONICS TECH GROUP CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com