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semiconductor storage device

A storage device and semiconductor technology, applied in the direction of information storage, static memory, read-only memory, etc., can solve the problems of time-consuming, increase of fuse read-only memory blocks, high misreading, etc.

Active Publication Date: 2018-11-02
KIOXIA CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, with the miniaturization of memory cells, the erase level tends to fluctuate, the difference between the erase level and the read level becomes smaller, and the possibility of misreading increases.
[0006] In addition, when the miniaturization of the memory unit progresses and the memory capacity increases, the number of blocks also increases, so the defective information that should be recorded in the ROM FUSE block also increases, so there is a possibility that the reading from the ROM FUSE block may be defective. information, but time-consuming

Method used

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no. 1 Embodiment approach

[0025] figure 1 It is a block diagram showing a schematic configuration of the semiconductor memory device 1 according to the first embodiment. figure 1 The semiconductor memory device 1 shown in FIG. 1 shows an example of a NAND type flash memory.

[0026] figure 1 The semiconductor memory device 1 has a cell array (cell array) 2, a low bit decoder 3, a word line driver 4, a column decoder 5, a sense amplifier (S / A) 6, a data latch circuit 7, a controller 8, a high Voltage generator 9 , address register 10 , command decoder 11 and I / O buffer 12 .

[0027] The cell array 2 has a NAND string 20 in which a plurality of memory cells are connected in series. figure 2 It is a block diagram showing a detailed structure around the cell array 2 . Such as figure 2 As shown, the cell array 2 is divided into a plurality of blocks (blocks) BLK0˜BLKn. In each block, a plurality of the above-mentioned NAND strings 20 are arranged in a column direction. Each NAND string 20 has a plu...

no. 2 Embodiment approach

[0055] In the second embodiment described below, when it is determined that the ROM FUSE block is defective, the ROM FUSE block is refreshed (refresh).

[0056] The NAND flash memory of the second embodiment has the figure 1 With the same block structure, the processing operation of the controller 8 is different from that of the first embodiment, so the processing operation of the controller 8 will be described below.

[0057] Figure 4 It is a flowchart showing the defect inspection process of the ROM FUSE block according to the second embodiment. First, a defect inspection of the ROM FUSE block is performed (step S11, first defect detection unit). In the defect inspection in step S11 , for example, the conventional block inspection described above is performed for memory cells on a specific word line in the ROM FUSE block. Alternatively, any one of the above-mentioned E-to-A detection methods 1 to 3 can also be used.

[0058] When judging in the step S11 that the ROM blo...

no. 3 Embodiment approach

[0074] In the third embodiment described below, it is automatically determined whether or not the ROM FUSE block has been refreshed in the past, and the ROM FUSE block that has been refreshed in the past is not re-refreshed.

[0075] The NAND flash memory of the third embodiment has the figure 1 With the same block structure, the processing operation of the controller 8 is different from that of the first and second embodiments, so the processing operation of the controller 8 will be described below.

[0076] Image 6 It is a flowchart showing the defect inspection process of the ROM FUSE block according to the third embodiment. First, data of memory cells on a specific word line in the ROM FUSE block is read (step S31).

[0077] All the memory cells of the unused segment on a specific word line are all "1". On the other hand, if all the memory cells of the unused segment on the specific word line in the ROM FUSE block that has not been refreshed are all written with "0" in...

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Abstract

A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor memory device capable of storing defective information. Background technique [0002] In some cases, a ROM FUSE block is provided in the memory cell array, and the ROM FUSE block stores defect information of memory cells in units of blocks or columns. [0003] The ROM FUSE block has the same size as a normal block and has a plurality of memory cells. When defects exceeding the allowable limit occur in the memory cells of the ROM FUSE block, the ROM FUSE data itself stored in the ROM FUSE block may also become defective. Furthermore, when a defect occurs in ROM FUSE data, it takes time to correct the error, and the operating speed of the semiconductor memory device may decrease. In particular, as memory cells are miniaturized, memory cells tend to be defective, and therefore, defect inspection of ROM FUSE blocks becomes important. [0004] The defect check of the ROM FUSE block is usually...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/00
CPCG11C29/76G11C11/406G11C16/00G11C16/349G11C29/021G11C29/028G11C29/24G11C2029/4402
Inventor 山口幸一郎御明诚志贺仁柴田升
Owner KIOXIA CORP