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Semiconductor memory

A memory and semiconductor technology, applied in the direction of semiconductor devices, static memory, read-only memory, etc., to achieve the effect of high-speed detection area and area saving

Active Publication Date: 2016-05-11
MEDIATEK INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In addition, the detection speed of traditional ViaROM and the local variation of devices (device local variation) need to be strengthened to meet the trend of high-speed ROM

Method used

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  • Semiconductor memory
  • Semiconductor memory
  • Semiconductor memory

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Experimental program
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Embodiment Construction

[0013] The specification and claims use certain terms to refer to particular components. Those skilled in the art can understand that manufacturers may use different names to refer to the same component. This document distinguishes components not by difference in name, but by difference in function. In the following description and claims, the word "comprises" is open-ended, so it should be read as "including, but not limited to...".

[0014] image 3 A circuit diagram of the semiconductor memory 300 according to the first embodiment of the present invention is shown. Each row of the semiconductor memory 300 includes 5 memory cells, that is, there are 20 memory cells in total, wherein the memory cells U00-U04 are in the first row (controlled by word line WL0); the semiconductor cells U10-U14 are in the second row ( controlled by word line WL1); memory cells U20-U24 are in the third row (controlled by word line WL2); memory cells U30-U34 are in the fourth row (controlled by ...

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PUM

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Abstract

The invention provides a semiconductor memory, which includes: a first switching transistor, wherein the first switching transistor has a first terminal, a second terminal, and a third terminal, and the second terminal is coupled to a first word-line; a first differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the first terminal of the first switching transistor for storing first information; and a second differential bit-line pair possessing a non-inverted bit-line and an inverted bit-line, wherein the non-inverted bit-line and the inverted bit-line thereof are mutually-exclusively coupled to the third terminal of the first switching transistor for storing second information.

Description

technical field [0001] Embodiments of the present invention relate to a semiconductor memory, especially a via-programmable read-only memory (Via-programmable Read-Only Memory, ViaROM), which does not have a dummy polysilicon gate (dummy polygate) and has a high Detection speed. Background technique [0002] figure 1 Shown in is a conventional ViaROM, which requires a dummy polysilicon gate for diffusion isolation, which shows a circuit schematic of a prior art 4x4ViaROM. Each transistor has a first terminal connected to a reference voltage (eg, ground voltage), and a second terminal connected to one of the four word lines. Most importantly, each transistor has a third terminal that stores data depending on whether that terminal is connected to one of the four bit lines via a via contact. Bitlines 0-3 are denoted "BL0-BL3" and wordlines 0-3 are denoted "WL0-WL3". figure 2 show figure 1 The circuit layout diagram of 4x4ViaROM in. Effective bit-cell size requires an ave...

Claims

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Application Information

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IPC IPC(8): G11C17/12
CPCG11C17/12G11C17/123G11C17/126H10B20/34
Inventor 王麒云
Owner MEDIATEK INC