A dram clock synchronization system

Abstract

The invention discloses a DRAM clock synchronizing system, comprising a receiver, a DLL delay chain, a DLL phase discriminator and a DLL control circuit, wherein an input clock signal line is connected with the input end of the receiver and the first input end of the DLL phase discriminator, the output end of the receiver is connected with the input end of the DLL delay chain, the output end of the DLL delay chain is connected with the second input end of the DLL phase discriminator, and the output end of the DLL phase discriminator is connected with the DLL delay chain via the DLL control circuit. According to the DRAM clock synchronizing system, a feedback circuit which can cause synchronization errors is eliminated in the prior art, the dps of the input clock and output clock directly enter the DLL phase discriminator, and when the DLL is locked, the rising edges of the two input clocks of the DLL phase discriminator are flush with each other, namely the rising edges of the input clock and the output clock are flush with each other. As the DRAM clock synchronizing system provided by the invention does not have the feedback circuit, the problem of matching of delay times does not exists, and the requirement of system clock synchronization can be met provided the DLL can be correctly locked.

Description

technical field [0001] The invention relates to the technical field of DRAM, in particular to a DRAM clock synchronization system. Background technique [0002] see figure 1 As shown, the working principle of DRAM system clock synchronization in the prior art is: [0003] The system requires the input clock to be aligned with the rising edge of the output dqX (X=0,1,2...n) and dqs, that is [0004] T1+T2+T3+T4=N*TCK N is an integer [0005] Among them, T1 is the delay time of the receiver rcv, T2 is the delay time of the DLL delay chain, T3 is the delay time of the clock tree, T4 is the delay time of the transmitter OCD, and TCK is the clock period. If the rising edges of the input clock and the output dqX and dqs are not aligned, errors will occur when the system reads data at high frequency. [0006] When the DLL is locked, the rising edges of the two input clocks of the DLL phase detector are aligned, that is [0007] T2+T5=N*TCK [0008] Among them, T5 is the delay...

AI Technical Summary

Problems solved by technology

[0011] For the consideration of power consumption, the feedback circuit is a simple copy of rcv, clock tree and OCD; so there are the following problems: if the voltage, temperature or process of the DRAM system changes, the delay time of the feedback circuit and the delay time of the real circuit deviation will occur, that is,

[0013] Then the rising edges of the input clock and the output dqX and dqs are not aligned, and the system will make errors when reading data when it is working at high frequency

Images