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soi device and its manufacturing method

A device and base substrate technology, applied in the field of semiconductor-on-insulator devices and their manufacturing, can solve the problems of reduced device performance, difficulty in controlling SOI layer thickness, and sensitivity to Si loss.

Active Publication Date: 2019-06-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This leads to difficulties in controlling the thickness of the SOI layer in the process and is too sensitive to Si loss
In addition, thin SOI layers increase external resistance and thus degrade device performance

Method used

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  • soi device and its manufacturing method
  • soi device and its manufacturing method
  • soi device and its manufacturing method

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Embodiment Construction

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0012] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention provides an SOI device and a manufacturing method therefor. According to an embodiment, the SOI device can comprise an SOI substrate, a semiconductor device, retrograde wells and back gates, wherein the SOI substrate comprises a base substrate, an embedded insulating layer and an SOI layer; the semiconductor device is formed on the SOI substrate; the semiconductor device comprises a source region and a drain region positioned in the SOI layer, and a channel region positioned between the source region and the drain region; the retrograde wells are formed in the SOI layer, and are positioned below the channel region, wherein the retrograde wells are arranged towards one side of the source region or the drain region; the back gates are formed in the base substrate; and the back gates and the retrograde wells are electrically coupled.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor-on-insulator (SOI) device with an asymmetric retrograde well (Retrograde Well, RW) and a back gate and a manufacturing method thereof. Background technique [0002] Fully depleted (FD) semiconductor-on-insulator (SOI) field effect transistor (FET) devices have several advantages, such as reduced power consumption and reduced leakage, among others. Since the warping (Kink) effect can be eliminated, the FD SOI device can well suppress the short channel effect and achieve a near-ideal subthreshold slope. [0003] However, FD SOI devices require very thin SOI layers, such as about 10-20 nm, to enable complete depletion. This leads to difficulties in controlling the thickness of the SOI layer in the process and is too sensitive to Si loss. Furthermore, thin SOI layers increase external resistance and thus degrade device performance. Contents of the i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L29/423H01L29/66H01L21/28
CPCH01L29/0649H01L29/0657H01L29/42356H01L29/66484H01L29/7831
Inventor 朱慧珑张严波钟健
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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