Trench-type super junction manufacturing method
A manufacturing method and super-junction technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as poor uniformity of reverse breakdown voltage
Active Publication Date: 2018-04-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
In the etching of trenches, the morphology of trenches in different regions of the same semiconductor substrate wafer is not completely the same, and the reverse breakdown voltage of super junction devices is greatly affected by the morphology of trenches, making Poor uniformity of reverse breakdown voltage of superjunction devices on the same wafer
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Embodiment Construction
[0034] Such as Figure 1A As shown, it is a schematic diagram of the structure of a super junction located in the edge region of the wafer formed by the existing trench-type super junction manufacturing method; as Figure 1B Shown is a schematic diagram of the structure of the super junction located in the middle region of the wafer formed by the existing trench-type super junction manufacturing method; the existing trench-type super junction manufacturing method includes the following steps:
[0035] Step 1. Provide a semiconductor substrate wafer 101, on the surface of the semiconductor substrate wafer 101, a first conductivity type epitaxial layer 102 is formed, and the N-type epitaxial layer 102 is taken as an example for illustration below;
[0036] Step 2, using a photolithography process to define a trench formation area and open the trench formation area; in the existing method, the size of the trenches at different positions on the semiconductor substrate wafer 101 is ...
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Abstract
The invention discloses a manufacturing method for a groove-type super junction. The manufacturing method comprises the following steps: step one, providing a wafer, wherein a first conduction type epitaxial layer is formed on the surface of the wafer; step two, using a photolithography technique to define a groove forming region and setting the size of top width of each groove on the wafer to be the same; step three, carrying out etching on the first conduction type epitaxial layer to form grooves; and step four, filling a second conduction type epitaxial layer in the grooves, setting the doping density of the epitaxial layer in the grooves of an internal region and an edge region respectively according to a relation curve of respective doping density and reverse breakdown voltage, and enabling the reverse breakdown voltage after doping to approach the maximum value in the corresponding relation curve. According to the manufacturing method, the in-plane uniformity of the reverse breakdown voltage of a super junction device on the same wafer can be improved, and the reverse breakdown voltage of the super junction device can be improved under the condition that the in-plane uniformity of the reverse breakdown voltage of the super junction device on the same wafer is higher.
Description
technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing method of a trench type super junction. Background technique [0002] The super junction is composed of alternately arranged P-type thin layers and N-type thin layers formed in the semiconductor substrate, and the depletion layer formed by matching the P-type thin layers and N-type thin layers is used to support the reverse withstand voltage. The existing super junction manufacturing method includes the manufacturing method of trench type super junction. This method is to manufacture super junction devices through trench technology. Etch a trench with a certain depth and width, and then fill the etched trench with P-type doped silicon epitaxy by means of epitaxial filling (ERIFilling). In the etching of trenches, the morphology of trenches in different regions of the same semiconductor substrate wafer is not completely the sa...
Claims
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IPC IPC(8): H01L21/265H01L21/336
CPCH01L21/26513H01L29/66477
Inventor 李昊
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP