A multi-threshold asymmetric configuration memory for single-event hardened FPGAs

Abstract

The invention discloses a multi-threshold asymmetric configuration memory used for a single-particle reinforcement FPGA (Field Programmable Gate Array). The configuration memory uses a plurality of MOS (Metal Oxide Semiconductor) tubes which have unequal threshold values and different breadth length ratios, and PMOS (P-channel Metal Oxide Semiconductor) tubes with a pull-up function, and the circuit, the domain and the technological parameters of the configuration memory are asymmetric to realize a purpose that the initial states of the configuration memory are all zero after the FPGA is powered on and before the FPGA is reset. The configuration memory consists of eight PMOS tubes and eight NMOS (N-channel Metal Oxide Semiconductor) tubes, wherein two of the eight PMOS tubes have high threshold values and the small breadth length ratio, and two groups independently adopt two PMOS tubes to form two circuits with the pull-up function; and two of another eight NMOS tubes have high threshold values and the small breadth length ratio. The configuration memory has the characteristics of multi-threshold asymmetry, the powered-on configuration memory has a certain initial value to prevent an interconnection matrix from generating competitive paths ''1'' and ''0'', and the power-on surging current of the FPGA is effectively eliminated.

Description

technical field [0001] The invention relates to a multi-threshold asymmetrical configuration memory for single-particle reinforcement FPGA, which is a configuration memory for eliminating the power-on surge current of FPGA, and belongs to the field of integrated circuits. Background technique [0002] A Field Programmable Logic Gate Array (hereinafter referred to as FPGA) can implement different logic functions according to configuration information. The SRAM type FPGA uses a configuration memory array composed of SRAM units to store user configuration information. The configuration frame composed of SRAM units can be programmed repeatedly indefinitely, making the FPGA application very flexible, especially suitable for aerospace engineering. The characteristic requirements of high reliability, multiple varieties, and small batches of devices are widely used in aerospace engineering. [0003] However, the initial logic state of the SRAM unit after power-on is randomly "0" or...

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