Multi-power cell and time distribution electrifying system of FPGA configuration memory array

Abstract

The invention discloses a multi-power cell and time distribution electrifying system of an FPGA configuration memory array. A memory cell of the FPGA configuration memory array is divided into a plurality of regions, the regions are sequentially electrified one by one, and therefore the electrifying surge current problem of a large-scale single-particle reinforcing SRAM type FPGA is effectively solved. When the FPGA is electrified, the regions are sequentially electrified through an electrifying control circuit, and therefore an electrifying peak current is decreased. The voltages outputted by all electrifying sub-circuits to the memory cell regions are simultaneously connected to an overall network in parallel, therefore, the voltages of all the memory cell regions of a whole FPGA chip are same, and the consistency is guaranteed. According to the multi-power cell and time distribution electrifying system of the FPGA configuration memory array, the electrifying surge current can be effectively eliminated, and meanwhile scale independence between the electrifying current and the FPGA is achieved by dividing the FPGA into multiple regions.

Description

technical field [0001] The invention relates to a multi-power partition time-sharing power-on system for an FPGA configuration memory array, which belongs to the technical field of integrated circuits. Background technique [0002] A Field Programmable Logic Gate Array (hereinafter referred to as FPGA) can implement different logic functions according to configuration information. The SRAM type FPGA uses a configuration memory array composed of SRAM units to store user configuration information. The configuration frame composed of SRAM units can be programmed repeatedly indefinitely, making the FPGA application very flexible, especially suitable for aerospace engineering. The characteristic requirements of high reliability, multiple varieties, and small batches of devices are widely used in aerospace engineering. [0003] In the prior art, power is supplied to all memory cells at the same time when the configuration memory array is powered on. The disadvantage is that the s...

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Problems solved by technology

[0003] In the prior art, power is supplied to all memory cells at the same time when the configuration memory array is powered on. The disadvantage is that the short-term power supply current will increase sharply, which is called "power-on surge current", and this current will increase with the size of the FPGA. increase by increasing

When designing a power supply circuit using an FPGA circuit system, the maximum current that the power supply circuit can provide must exceed the power-on surge current, which means that the actual power supply capacity of the power supply circuit is much greater than the normal operation of the FPGA, resulting in a lot of waste

In addition, the sharp high current impact will also reduce the reliability of FPGA devices and systems

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