MOS tube parameter degradation detection circuit

A technology of MOS tube and parameter degradation, applied in the direction of measuring electricity, measuring electrical variables, measuring devices, etc., can solve problems such as MOS tube parameter degradation

Active Publication Date: 2016-07-13
FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Based on this, it is necessary to provide a detection circuit for MOS tube paramet

Method used

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  • MOS tube parameter degradation detection circuit
  • MOS tube parameter degradation detection circuit
  • MOS tube parameter degradation detection circuit

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Embodiment Construction

[0017] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, and do not limit the protection scope of the present invention.

[0018] see figure 1 Shown is an embodiment of the detection circuit for MOS tube parameter degradation of the present invention. The detection circuit of the MOS transistor parameter degradation in this embodiment includes a stress test circuit 100, a standard clock input circuit 200, a sampling circuit 300, a sampling counter 400, a clock counter 500 and a processor 600;

[0019] Stress test circuit 100, standard clock input circuit 200 are connected with sampling circuit 300 respectively, and sampling circuit 300 is connected with sampling counter 400, and sampling co...

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Abstract

The invention relates to an MOS tube parameter degradation detection circuit comprising a stress test circuit, a standard clock input circuit, a sampling circuit, a sampling counter, a clock counter, a controller, and a processor. In the MOS tube parameter degradation detection circuit, the stress test circuit outputs a test signal characterizing the parameters of an MOS tube in the stress test circuit, the sampling circuit acquires sampling data according to the test signal, the sampling counter carries out counting according to the sampling data, the standard clock input circuit provides clock signals for the sampling circuit and the clock counter, the clock counter counts the clock signals, and the processor carries out calculation according to the count value of the sampling data and the count value of the clock signals to get the detection value of MOS tube parameter degradation. The detection circuit can complete detection of related values of MOS tube parameter degradation according to the composition thereof without the need for external equipment, the application scope of the detection circuit is improved effectively, and the requirement of online monitoring is satisfied.

Description

technical field [0001] The invention relates to the technical field of MOS tube detection circuits, in particular to a detection circuit for MOS tube parameter degradation. Background technique [0002] With the development of VLSI manufacturing technology towards the nanometer direction, the size and feature size of the device is getting smaller and smaller, but its normal operating voltage has not been proportionally reduced, resulting in an increasing local electric field inside the device channel. Carriers in the channel are easy to obtain greater energy in a strong electric field to form hot carriers. The energy of hot carriers is high, and they exist in the device channel, easily cross the interface barrier, inject into the gate oxide layer, be captured by the charge trap in the gate oxide layer or in Si-SiO 2 The interface produces an interface state, which causes changes in relevant parameters of the device, such as threshold voltage, transconductance, and drain cur...

Claims

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Application Information

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IPC IPC(8): G01R31/26
CPCG01R31/2621
Inventor 雷登云陈义强侯波何春华黄云恩云飞
Owner FIFTH ELECTRONICS RES INST OF MINIST OF IND & INFORMATION TECH
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