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An Intelligent Refresh Control Method Based on Code Stream Preprocessing

A control method and preprocessing technology, applied in the field of integrated circuits, can solve the problems of complex implementation, poor practicability, and low refresh efficiency, and achieve the effect of compressing the amount of data, simple and convenient implementation methods, and easy implementation

Active Publication Date: 2018-11-06
BEIJING MXTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Frame-by-frame refresh is to refresh the complete code stream into the FPGA to be refreshed frame by frame. This refresh method is simple to implement, but due to a large amount of meaningless data in the code stream, the refresh efficiency is low; Read the code stream in the FPGA to be refreshed, compare the read-back code stream with the correct code stream frame by frame, detect the wrong code stream data frame, and refresh only the wrong code stream data frame Correction, because this method needs to read back the FPGA to be refreshed, the implementation is complicated, and the actual refresh frequency is close to the frame-by-frame refresh frequency, so the practicability is not strong

Method used

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  • An Intelligent Refresh Control Method Based on Code Stream Preprocessing
  • An Intelligent Refresh Control Method Based on Code Stream Preprocessing
  • An Intelligent Refresh Control Method Based on Code Stream Preprocessing

Examples

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Embodiment

[0068] Taking refreshing the XC2V1000 FPGA produced by Xilinx as an example, when using the method of the present invention to refresh, first read back the ID code through the JTAG port or SelectMAP, identify it as an XC2V1000 FPGA, and determine that the data length of one frame is 32*106bits , the length of the complete code stream is 4089504bits; read the complete code stream from the memory, configure the XC2V1000, and process the code stream at the same time, the effective code stream data is: i-th frame data {0011...0110}, i+ 1 frame of data {1001...0100}, the i+5th frame of data {0000...1000}, these data are represented as {i, 0011...0110}, {i+1, 1001...0100}, {i+ 5. The format of 0000...1000} is sequentially stored in the position after 4089504 bits in the memory, and the special data {0,665599AA...} that marks the end is written; when refreshing, read the data in the position after 4089504 bits in the memory, The first thing to read is {i, 0011...0110}, {i+1, 1001...0...

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Abstract

The invention relates to an intelligent refreshing control method based on code stream preprocessing.The method is achieved through a refreshing control system which comprises a code stream memory, a refreshing module and an FPGA; the refreshing module reads code streams in the code stream memory and screens data frames of the code streams in real time to remove invalid code stream data frames and write the remaining valid code stream data frames in remaining space of the code stream memory in real time, and when refreshing is needed, the refreshing module reads the valid code stream data frames in the code stream memory to refresh the FPGA.According to the method, the invalid data is completely removed before the FPGA is refreshed, only the valid data is refreshed, the transmitted data volume during refreshing is significantly decreased, therefore, the actual refreshing period can be effectively shortened on the premise that the refreshing basic frequency of a clock is not increased, the actual refreshing frequency is increased, and then the anti-single particle turnover capacity of an SRAM-type FPGA device to be refreshed is improved.

Description

technical field [0001] The invention relates to an intelligent refresh control method based on code stream preprocessing, which is particularly suitable for recovering the space single-event flip fault occurred in the SRAM type FPGA used for aerospace, and belongs to the technical field of integrated circuits. Background technique [0002] The basic structure of SRAM FPGA is as follows: Figure 5 , where the main functional modules include: input and output blocks (IOB) around the circle, two columns of block memory (BRAM) on the edge, and internal programmable logic block array (CLB). In addition, there are connections throughout the entire circuit. The interconnection resource of the module. The above logic resources and interconnect resources are all controlled by the underlying SRAM configuration bits. A large number of SRAM configuration bits distributed throughout the FPGA circuit determine the specific functions of the FPGA circuit, and the set of bit streams of thes...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/07
CPCG06F11/0703
Inventor 李学武张帆郑咸剑姜爽李琦于晓华肖阳贾瑾
Owner BEIJING MXTRONICS CORP
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