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Scheduling and traffic management with offload processors

A technology of processors and scheduling systems, which is used in electrical digital data processing, instruments, memory systems, etc.

Inactive Publication Date: 2016-07-13
XOCKETS IP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Without an efficient mechanism for scheduling packet processing arriving as part of a complex data flow system, users may experience unacceptable delays in network system response

Method used

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  • Scheduling and traffic management with offload processors
  • Scheduling and traffic management with offload processors
  • Scheduling and traffic management with offload processors

Examples

Experimental program
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Embodiment Construction

[0016] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Embodiments illustrate processing systems and methods for scheduling packet flows in a packet processing system. Such scheduling may be performed by or by virtue of an offload module connected to the system's memory bus. Such offload processors may be added to any host processor connected to the system memory bus, and, in some embodiments, such offload processors may process data transferred on the system memory bus independently of any host processor. grouping. In very specific embodiments, the processing modules may populate physical sockets for connecting in-line memory modules (eg, DIMMs) to the system memory bus.

[0017] Figure 1-0 is a diagram of a system 100 for providing scheduling and traffic management services. The system 100 may include a switch 106, a host processor section 108 / 110, a memory controller 112, and an offload processor section ...

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Abstract

A scheduling system for a packet processing system is disclosed. The system can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input / output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input / output queues and placing the reordered network packets into second multiple input / output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input / output queues to multiple output ports, and multiple offload processors, with each of the offload processors being coupled to at least one of the multiple output ports, and the offload processors being configured to modify the network packets.

Description

technical field [0001] The described embodiments relate to scheduling and traffic management services for computer systems that may be provided by memory bus connected modules with offloaded processors. Background technique [0002] Efficient management and processing of network packet flows is critical to high performance networked computing systems. Depending on hardware configuration, process flow, and data flow, network packet flow can be highly variable, and data processing requirements vary across orders of magnitude timescales that can range from seconds to hours. Substantial improvements in network services may be enabled by a system that flexibly processes data flows, identifies or characterizes patterns in the data flows, and improves routing and processing decisions on the data flows. This is especially important in networked computer environments using packet switched communications. For example, delays are often introduced in the data stream due to packet insp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/26H04L47/56
CPCH04L47/624H04L47/2441H04L67/1097H04L67/10G06F13/4022G06F13/285G06F13/1652G06F13/16G06F13/362H04L47/56H04L47/6295H04L49/90G06F13/4068G06F12/1081G06F2212/1024G06F12/1027Y02D10/00H04L2101/686H04L47/193G06F9/4843G06F12/0815G06F12/0875G06F9/461G06F9/3877G06F15/161G06F15/17337H04L49/40H04L61/103H04L61/2592
Inventor P·达拉尔S·贝莱尔
Owner XOCKETS IP