Scheduling and traffic management with offload processors
A technology of processors and scheduling systems, which is used in electrical digital data processing, instruments, memory systems, etc.
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[0016] Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Embodiments illustrate processing systems and methods for scheduling packet flows in a packet processing system. Such scheduling may be performed by or by virtue of an offload module connected to the system's memory bus. Such offload processors may be added to any host processor connected to the system memory bus, and, in some embodiments, such offload processors may process data transferred on the system memory bus independently of any host processor. grouping. In very specific embodiments, the processing modules may populate physical sockets for connecting in-line memory modules (eg, DIMMs) to the system memory bus.
[0017] Figure 1-0 is a diagram of a system 100 for providing scheduling and traffic management services. The system 100 may include a switch 106, a host processor section 108 / 110, a memory controller 112, and an offload processor section ...
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