ASIC (Application Specific Integrated Circuit) design clock network reconfiguring system and method

Abstract

The invention discloses an ASIC (Application Specific Integrated Circuit) design clock network reconfiguring system and method. The system comprises a clock node analyzing and anchoring unit which is used for analyzing a clock network structure in an ASIC front-end netlist on the basis of a reconfiguration file, obtaining an analysis result and anchoring to-be-modified network nodes in the clock network structure; a test clock inserting unit which is used for respectively modifying the to-be-modified network nodes to obtain a modified ASIC design clock network structure; a clock connection reconfiguring unit which is used for adjusting the specific clock connection in the modified ASIC design clock network structure on the basis of the analysis result to obtain a reconfigured clock network structure; and a reconfigured clock network outputting unit which is used for outputting a report file of the reconfigured clock network structure and a reconfigured ASIC design netlist. The system disclosed by the invention has the advantages that a unified planning and adjusting platform is provided for the modification of the clock network in the ASIC design back-end process; the design reworking is greatly reduced; and the overall development efficiency is increased.

Description

technical field [0001] The invention relates to the technical field of clock network reconfiguration, in particular to an ASIC design clock network reconfiguration system and method. Background technique [0002] In the back-end process of ASIC design, there are many stages that need to analyze and modify the clock network of the front-end netlist. For example, it is common to make appropriate adjustments to the clock network in the front-end netlist in the testability design and layout and routing stages of the ASIC design back-end process. In the testability design stage, it is necessary to distinguish between low-speed tests and high-speed tests according to test categories; In the automatic layout and routing stage, it is necessary to establish clock trees for different clock domains, and sometimes it is even necessary to distinguish the standard cell clock network from the memory bank and IP core clock network. However, the clock network is the backbone of the entire A...

AI Technical Summary

Problems solved by technology

However, the clock network is the backbone of the entire ASIC design. Phased and fragmented changes will cause difficulties in many aspects of the ASIC back-end design process, greatly increasing the resulting design rework, reducing the overall R&D efficiency, and even will affect the performance of the system

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