Method and system for optimizing layout design rules

A layout design and optimization method technology, applied in design optimization/simulation, CAD circuit design, calculation, etc., can solve problems such as the growth of hot spots in the wiring layer, unsatisfactory results, and difficulties in the design process, so as to optimize design rules and shorten Design cycle, strong feasibility effect

Active Publication Date: 2016-08-03
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0004] In the research and development of advanced technology nodes, design graphics are greatly limited in terms of geometry and variability. Traditional design rules are no longer applicable, and layout types that are not suitable for manufacturing in standard cells have also greatly increased. The hotspot area has also increased in a large proportion, and there are many problems that need to be solved. If the traditional method of simulation optimization through the test layout is used, it is difficult to continue the optimization, and it is impossible to obtain satisfactory results, which makes the design process extremely difficult. The cycle is too long

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  • Method and system for optimizing layout design rules
  • Method and system for optimizing layout design rules

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Embodiment Construction

[0054]In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0055] In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

[0056] refer to figure 1 As shown, the present invention proposes a method for optimizing layout design rules, including:

[0057] S01, providing an initial layout including initial design rules;

[0058] S02, splitting the initial layout into key graphics to obtain a key graphics layout, using at least part o...

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Abstract

The invention provides a method for optimizing layout design rules, wherein aiming at research and development of advanced technological nodes, an initial layout is split from an initial layout, and the key graph is taken as a layout for subsequent simulation optimization; during the optimization, through combination of a light source masking and optimization simulation, a rational light source, a matched masking template and an optimized photo-etching optical model are determined; then, under the photo-etching optical model, manufacturability of the optimized light source and the optimized masking template is simulated; the design rules are optimized according to hotspot output of the manufacturability simulation; and the optimized design rules are obtained through repeated iterations. During the optimization, the key graph layout is optimized, so that feasibility and optimization efficiency are high. Through adjustment of the design rules, the quantity of iterations in the layout simulation can be reduced and the optimization efficiency can be increased on one side; and on the other side, the more optimal design rules can be obtained, design courses are simplified, and design duration is shortened.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method and system for optimizing layout design rules. Background technique [0002] With the continuous development of science and technology, higher requirements are put forward for the performance and integration of integrated circuits, which has also become a rapid driving force for the development, configuration and manufacture of integrated circuits. According to Moore's Law, the current traditional semiconductor devices have entered the advanced technology node of 10nm and below, which poses challenges to the design and manufacturing process of integrated circuits. [0003] In the layout design and process development of advanced technology nodes, the idea of ​​joint design and process optimization (DTCO) is proposed. It is hoped that designers and technicians can cooperate well in development and provide more reasonable development for advanced technology nodes. ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/20G06F30/39
Inventor 苏晓菁陈颖段英丽韦亚一
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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